Resume.html

Polybus Systems Corporation

B. Joshua Rosen

23 Providence Road

Westford, MA 01886

Home (978) 692-4828

Cell (978) 828-0944

bjrosen@polybus.com

Mr. Rosen is a Xilinx XPERTs partner, for more details see: Xilinx XPERTS Program.

Overview

Mr. Rosen has extensive experience as an architect and designer of complex systems including mini-computers, super-computers, video systems and networking systems. Mr. Rosen has designed FPGAs and ASICs using both Verilog and VHDL. In addition Mr. Rosen has significant software development experience using C, assembly language and microcode.

Services

ASIC and FPGA Design (Verilog or VHDL)
Hardware Architecture

Project History
Technology Background
Employment History
Education
Patents

Project History
Project	Client/Employer	Technology
Data Acquisition for Power System Test Equipment	Doble Engineering	Spartan 3
InfiniBand Link Layer Core	unannounced	Xilinx Virtex2P/ASIC
Xilinx Virtex2 Test Patterns	Mentor Graphics	Xilinx Virtex2
SKYChannel to FPDP Bridge	Sky Computers	Xilinx Virtex2
OC48 SONET Alignment Processor	Agere Systems	Altera Stratix
Xilinx Spartan 2 Test Patterns	Netezza	Xilinx Spartan 2
InfiniBand Parallel Processor	Sky Computers	Off the shelf HCAs and Switches
InfiniBand To Sky Channel Bridge	Sky Computers	Virtex2
LANShare Media Server System	Avid Technology	Off the shelf boards
SDRAM Unit for low power DSP chip	Chipwrights Inc	ASIC
SGEN FPGA for a Router	Unisphere Networks	Xilinx Virtex
Queue Management Unit for the CPORT Distributed Communication Processor	CPort Corp	ASIC
ADSL ASIC Emulator	Aware, Inc.	Xilinx 4062xl
PCI to Slow PCI Bridge	IKOS Systems	Xilinx 4028xl
FPGA Test Patterns for ASIC Emulator	IKOS Systems	Xilinx 5200, 4013e, 4036xl and 4062xl,Virtex XCV800, Virtex XCV2000E
8 Port Fast Ethernet Switch	3Com	Xilinx 4000e and 4000ex
2 Port Fast Ethernet Switch	3Com	Xilinx 4000e
Peace of Mind End User Macintosh Diagnostic	Polybus Systems	Software
Wavelet Based Video Compression Board	Avid Technology	DSPs, and Xilinx FPGAs
Broadcast Quality JPEG Video Compression Board	Avid Technology	PALs, CCube JPEG chip
JPEG Video Compression Board	Avid Technology	PALs, CCube JPEG chip
Data Compression Board for a High Resolution Scanner	Optronics Division of Intergraph	Xilinx 3000 Series
Elementary Function Library	Kendall Square Research	Software
Floating Point Processor Chip	Kendall Square Research	ASIC
uFX Mini Super Computer	Alliant Computer Systems	ASIC
FX8 Mini Super Computer	Alliant Computer Systems	Gate Arrays
APU Super Mini Computer	ComputerVision	PALs and TTL
MV8000 Super Mini Computer	Data General	PALs and TTL

Technology Background

Mr. Rosen has extensive experience designing ASICs and FPGAs with Verilog and VHDL. Experienced with NCVerlog, VCS, Finsim, Synopsys Design Compiler, and Synplify. In addition to his hardware skills, Mr. Rosen is proficient in C, assembly language and microcode

Employment History

Doble Engineering

Consultant Dec 2003, to Present

Developed a set of Spartan 3 FPGAs for use in power systems test equipment. The FPGAs captured data from multiple 100MHz AtoD converters and stored it in DDR RAM where it was accessible from an Motorola PPC over the PPCs local bus interface.

Unannounced (West Coast client)

IP development July 2003, to Present

Developed an InfiniBand Link Layer Core. The core implements the full link layer specified by the InfiniBand Architecture spec version 1.1. It operates at both 1X and 4X speeds, has very low latency and runs in a Viretex2P –5. The core is available for license from Polybus, http://www.polybus.com/ib_link_layer_website.

Mentor Graphics

Consultant Feb 2003, to Present

Developed a comprehensive set of FPGA test patterns for the Xilinx XC2V6000 FPGA and integrated them in to the test suite for the Mentor’s ASIC emulator system. The test patterns are available for license from Polybus, http://www.polybus.com/xilinx_test_patterns/.

Agere Systems

Consultant Mar 2002, to November 2002

Developed an OC48 SONET alignment processor. The processor provides up to 250ms of delay compensation on each of 48 SONET tributaries and time aligns the channels into from one to 48 groups. The processor included a DDR interface and was implemented in a Altera Stratix FPGA.

Netezza, Framingham MA

IP development Aug 2002, to Nov 2002 (Spartan 2), 2003 (Spartan 2e 300), 2004 (Spartan 2e 400)

Developed a complete set of FPGA test patterns for the Xilinx Spartan 2 and 2e. The FPGA test patterns are available for license from Polybus, http://www.polybus.com/xilinx_test_patterns/.

Sky Computers, Chelmsford MA

Consultant Nov 2002, to Sept 2003

SKYChannel to FPDP bridge FPGA. The FPGA connects SKY Computer’s parallel processor interconnect system to a Front Panel Data Port (FPDP) bus.

Consultant June 2001 to Dec 2002

Wrote the architecture specification, defined the protocols and wrote the Verilog for an InfiniBand to Sky Channel bridge FPGA. The FPGA bridges the proprietary Sky Channel multiprocessor interconnect to InfiniBand.

Following the bridge project was responsible for defining the architecture of a pure InfiniBand based parallel processor using off the shelf HCAs and switches.

Chipwrights Inc, Newton MA

Consultant Jan 2001 to June 2001

Designed the memory subsystem for Chipwright's Video and Imaging DSP. The SDRAM unit is optimized for streaming data, performing prefetch and caching operations to insure a continuous stream of data to the vector unit.

Unisphere Networks, Westford MA

Consultant Jan 2000 to Jan 2001

FPGA Design for SGEN, SRM and XCM boards for Unisphere's core router.

CPort Corp., North Andover MA (now part of Motorola)

Consultant Jan 1999 to June 1999

ASIC design. Designed the queue management unit of the CPORT distributed communication processor.

Aware Inc., Bedford, MA

Consultant 1997 to Dec. 1998

Designed a PCI based Emulator for an ADSL ASIC. The emulator is a target mode PCI device based on 12 large Xilinx FPGAs. Wrote a partitioner which spreads the ASIC gates across the emulator.

IKOS Systems San Jose, CA

Consultant Feb. 1995 to Present

Wrote the fault isolation system for five generations of IKOS ASIC emulators. IKOS ASIC emulator utilize 300-400 large Xilinx FPGAs to emulate ASICs of up to 12 Million gates (VLE12M system released Dec 2000). My fault isolation software/verilog firmware identifies both interconnect failures (opens, shorts, bad drivers, bad receivers) and FPGA internal failures. The system consists of hundreds of verilog designs combined with C analysis code.

Designed a PCI to slow PCI bridge. The VirtualPCI is an FPGA based bridge that connects a full speed PC to an IKOS ASIC emulator running at a reduced speed (typically 1 MHz or less). The Virtual PCI handles both target and initiator mode transactions.

3Com Corporation Boxborough, MA

Consultant Feb. 1995 to May 1997

1996: Designed an 8 Port Fast Ethernet Local Switch for the Lanplex 6000, increasing the number of 100 BaseX ports supported by the Lanplex 6000 from 22 to 88 and increasing the available system bandwidth by as much as 8x (typically 3 to 4X). The local switch is based on a Xilinx 4036EX FPGA, which contains an address cache, datapaths and all of the control logic to manage the local traffic between the 8 ports as well as traffic to the other boards in the Lanplex 6000.

1995: Designed a 100 BaseX Ethernet adapter card for 3Com's Lanplex 2000 and 6000 switching products.

Avid Technology Burlington, MA

Consultant Dec. 1990 to July 1991 ,Jan. 1992 to May 1992, Dec. 1993 to Dec 1994, Jan 2001-Dec 2001

Designed a real time video compression/expansion board for the Macintosh based on the CCUBE CL550B JPEG chip. The board performs compression and expansion of 640 x 480 video images at a rate of 60 fields/second. Design of the board began during the last week of December, 1990 and was demonstrated at the National Association of Broadcasters show in April 1991. Full production began in June 1991. In 1992 designed a second generation board that improved picture quality from 'VHS' quality to full broadcast quality. The second generation board was introduced at the 1992 NAB show. In 1994 designed a multiple DSP based research board.

In addition to designing the hardware, Mr. Rosen wrote two Macintosh applications to support the product. The first application is a diagnostic suite which isolates faults to a single chip and displays the results graphically. The second application is a JPEG table editor which allows the user to edit four separate sets of JPEG tables and to compare the resulting pictures on the video screen side by side.

In 2001 developed the LANShare Media Server, an IDE based storages system optimized for streaming media applications.

Polybus Systems Corporation. Westford, MA

Vice President April 1989 to Present

Co-founded Polybus Systems Corporation for the purpose of designing a highly parallel 120 gigaflop supercomputer. Developed a business plan, a five year financial model, and a chip level partition of the system. Polybus was unable to secure funding for the system and switched to the Macintosh software market.

Developed 'Peace of Mind', an end user hardware diagnostic for the Macintosh family. Peace of Mind was launched at MacWorld Boston in August of 1992. MacWeek picked it as the top Rated Product in it's category. As well as being offered as an end user product, Peace of Mind was also being used by manufacturers as a manufacturing diagnostic platform. Products that use Peace of Mind include SuperMac's video boards and the Apple Duo MiniDoc. Peace of Mind was sold to Diagsoft Corp, Scotts Valley, CA, at the end of 1993.

Optronics Division of Intergraph Corporation Chelmsford,MA

Consultant July 1990 to Jan 1991

Designed a controller/data compression board for a high resolution, 2000 DPI, drum scanner. The design is based on Xilinx field programmable gate arrays and PALs. As part of the design effort, wrote a LISP based CAE system which generated netlist (XNF) and palasm file for the Xilinx tool set (XACT), ABEL files for the PALs, and a C model of the system. The CAE system accepts input in it's native format, in ABEL and in Palasm.

Kendall Square Research Waltham, MA

Consultant April 1988 to April 1989

Designed a floating point chip for KSR's parallel supercomputer and wrote an assembly language elementary function library for the Fortran and C compilers. The execution unit is a custom CMOS chip which executes two double precision floating point operations per cycle.

Alliant Computer Systems Littleton, MA

Hardware Architect November 1982 to March 1988

Employee number four, the first non-founder hired at Alliant. Responsible for hiring much of the original design team. Defined the basic organization of the first generation CE (computational element) used in the Alliant FX/8 parallel/vector mini-supercomputer. Designed several of the CE gate arrays, specifically the integer unit, the integer multiplier and the floating point divider/square rooter.

Hardware architect of the FX, a VLSI version of the Alliant FX architecture. Initiated the program, partitioned the CPU chipset, defined the performance objectives and served as one of the technical leaders of the project.

Computervision Corporation Bedford, MA

Manager of Processor Development 1979 to 1982

As Manager of Processor Development was responsible for a group of engineers and technicians. The processor group designed and developed 32 bit super-minicomputers for use in analytical and engineering applications.

Prior to serving as manager of processor development, was the architect and principal designer of the Computervision APU, a 32 bit processor targeted at the CAD/CAM market. Defined the basic system organization, wrote the architecture specification and designed the integer/address and floating point boards.

Data General Corporation Westboro, MA

Design Engineer 1976 to 1979

Designed the arithmetic unit for the Eclipse MV 8000, Data General's first 32 bit computer. Featured in the book 'Soul of a New Machine'.

Prior to joining the Eclipse group, was a member of the Special Systems Division. While in Special Systems designed a single board array processor, a 16 terminal video controller, a word processor, and the receiver section of a large synchronous communication network.