accblock.vhd

library IEEE;

use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity accblock is

port (

a :buffer std_logic_vector (45 downto 0);
clkenb :in std_logic;
gblreset :in std_logic;
sysclk :in std_logic

);
end accblock;

architecture BEHAVIOR of accblock is

component acc46

port (

clkenb : in std_logic;
sysclk : in std_logic;
gblreset : in std_logic;
a : in std_logic_vector (45 downto 0);
b : in std_logic_vector (45 downto 0);
y : buffer std_logic_vector (45 downto 0)

);

end component;


-- signals begin here

signal b : std_logic_vector (45 downto 0);
signal c : std_logic_vector (45 downto 0);
signal d : std_logic_vector (45 downto 0);
signal e : std_logic_vector (45 downto 0);
signal f : std_logic_vector (45 downto 0);
signal g : std_logic_vector (45 downto 0);
signal h : std_logic_vector (45 downto 0);
signal i : std_logic_vector (45 downto 0);
signal j : std_logic_vector (45 downto 0);
signal k : std_logic_vector (45 downto 0);




begin



acc46_1: acc46

port map (

clkenb => clkenb,
sysclk => sysclk,
gblreset => gblreset,
a (45 downto 0) => b (45 downto 0),
b (45 downto 0) => e (45 downto 0),
y (45 downto 0) => a (45 downto 0)

);

acc46_2: acc46

port map (

clkenb => clkenb,
sysclk => sysclk,
gblreset => gblreset,
a (45 downto 0) => a (45 downto 0),
b (45 downto 0) => c (45 downto 0),
y (45 downto 1) => b (44 downto 0),
y(0) => b(45)

);

acc46_3: acc46

port map (

clkenb => clkenb,
sysclk => sysclk,
gblreset => gblreset,
a (45 downto 0) => b (45 downto 0),
b (45 downto 0) => d (45 downto 0),
y (45 downto 2) => c (43 downto 0),
y (1 downto 0) => c (45 downto 44)

);

acc46_4: acc46

port map (

clkenb => clkenb,
sysclk => sysclk,
gblreset => gblreset,
a (45 downto 0) => c (45 downto 0),
b (45 downto 0) => e (45 downto 0),
y (45 downto 3) => d (42 downto 0),
y (2 downto 0) => d (45 downto 43)

);

acc46_5: acc46

port map (

clkenb => clkenb,
sysclk => sysclk,
gblreset => gblreset,
a (45 downto 0) => d (45 downto 0),
b (45 downto 0) => f (45 downto 0),
y (45 downto 4) => e (41 downto 0),
y (3 downto 0) => e (45 downto 42)

);

acc46_6: acc46

port map (

clkenb => clkenb,
sysclk => sysclk,
gblreset => gblreset,
a (45 downto 0) => e (45 downto 0),
b (45 downto 0) => g (45 downto 0),
y (45 downto 3) => f (42 downto 0),
y (2 downto 0) => f (45 downto 43)

);

acc46_7: acc46

port map (

clkenb => clkenb,
sysclk => sysclk,
gblreset => gblreset,
a (45 downto 0) => f (45 downto 0),
b (45 downto 0) => h (45 downto 0),
y (45 downto 2) => g (43 downto 0),
y (1 downto 0) => g (45 downto 44)

);

acc46_8: acc46

port map (

clkenb => clkenb,
sysclk => sysclk,
gblreset => gblreset,
a (45 downto 0) => g (45 downto 0),
b (45 downto 0) => i (45 downto 0),
y (45 downto 1) => h (44 downto 0),
y(0) => h(45)

);

acc46_9: acc46

port map (

clkenb => clkenb,
sysclk => sysclk,
gblreset => gblreset,
a (45 downto 0) => h (45 downto 0),
b (45 downto 0) => j (45 downto 0),
y (45 downto 0) => i (45 downto 0)

);

acc46_10: acc46

port map (

clkenb => clkenb,
sysclk => sysclk,
gblreset => gblreset,
a (45 downto 0) => i (45 downto 0),
b (45 downto 0) => k (45 downto 0),
y (45 downto 1) => j (44 downto 0),
y(0) => j(45)

);

acc46_11: acc46

port map (

clkenb => clkenb,
sysclk => sysclk,
gblreset => gblreset,
a (45 downto 0) => g (45 downto 0),
b (45 downto 0) => j (45 downto 0),
y (45 downto 2) => k (43 downto 0),
y (1 downto 0) => k (45 downto 44)

);
end;


library work;

configuration accblock_config of accblock is

for BEHAVIOR

for all: acc46 use entity work.acc46(BEHAVIOR); end for;

end for;
end accblock_config;

HDLMaker Generated Files
accblock.job Synopsys script file