| name.vhd | VHDL file |
| name.v | Verilog file |
| name.Make | Synopsys Makefile |
| name.job | Synopsys script |
| name.prj | Synplicity project file |
| name_lf.Make | Leapfrog Makefile |
| name_lf.cmd | Leapfrom Script |
| name_mt.do | Model Tech Script |
| name_v.cmd | Verilog Script |
| name.error | DRC file |
| name.pinlist | Pin cross reference for people to real, pins are sorted both by name and by pin number |
| name.rpt | Report file contains loading information for all signals |
| name.conn | Default connection file |
| name.xref | Pin cross reference (used when converting a pcb netlist to VHDL or Verilog) |
| name_batch.Make | Batch Synopsys Makefile |