Synthesis

<body topmargin=0 leftmargin=0 marginheight=0 marginwidth=0> <table cellpadding=0 cellspacing=0 border=0><tr> <td valign="top" colspan=2 height=90 BGCOLOR="#CC9900" TEXT="#080000" bgproperties="fixed" background="045005a0dwnjzk.gif"> <div> <A HREF="index.htm" TARGET="_top" TITLE="HDLmaker"><U><B>home</B></U></A><B>     | </B><B> </B><B> </B><B>  </B><FONT SIZE="5" COLOR="#FFCC66" FACE="Arial" ><B>HDLmaker</B></FONT></div> <div> <A HREF="id22.htm" TARGET="_top" TITLE="Top Files"><U><B>Top Files</B></U></A><B>   |   </B><A HREF="id23.htm" TARGET="_top" TITLE="Pin Files"><U><B>Pin Files</B></U></A><B>   |   </B><A HREF="id24.htm" TARGET="_top" TITLE="Language"><U><B>Language</B></U></A><B>   |   </B><A HREF="id28.htm" TARGET="_top" TITLE="Directory Organization"><U><B>Directory Organization</B></U></A><B>   |   </B><A HREF="id29.htm" TARGET="_top" TITLE="Simulation"><U><B>Simulation</B></U></A><B>   |   </B><B>Synthesis</B><B>   |   </B><A HREF="id33.htm" TARGET="_top" TITLE="Xilinx Tools"><U><B>Xilinx Tools</B></U></A><B>   |   </B><A HREF="id25.htm" TARGET="_top" TITLE="Examples"><U><B>Examples</B></U></A></div> <div> </div> </td> </tr><tr> <td valign="top" width=210 BGCOLOR="#FFFFFF" TEXT="#080000"> <div> Synthesis</div> <div> <B><IMG SRC="06569830.gif" border=0 width="105" height="131" ALIGN="BOTTOM" HSPACE="0" VSPACE="0"></B><A HREF="http://www.polybus.com" TARGET="_top" TITLE="http://www.polybus.com"><U><B>Polybus</B></U></A></div> <bR> <div> <A HREF="id30_m.htm#synplify" TARGET="TRLX_Middle" TITLE="Synthesis"><U><B>Synplify</B></U></A></div> <div> <A HREF="id30_m.htm#synplicity_top_file_directives" TARGET="TRLX_Middle" TITLE="Synthesis"><U><B>Synplify Directives</B></U></A></div> <div> <A HREF="id30_m.htm#synopsys_directives" TARGET="TRLX_Middle" TITLE="Synthesis"><U><B>Synopsys Directives</B></U></A></div> <div> <A HREF="id30_m.htm#common_directives" TARGET="TRLX_Middle" TITLE="Synthesis"><U><B>Common Directives</B></U></A></div> <div> <A HREF="id30_m.htm#precision" TARGET="TRLX_Middle" TITLE="Synthesis"><U><B>Precision</B></U></A></div> </td> <td valign="top" height=390 BGCOLOR="#FFFFFF" TEXT="#080000"> <div> HDLmaker supports Synplify, Synopsys and Exemplar. Synplify has the best support, Synopsys Design Compiler and FPGA compiler are well supported, only minimal, and possibly outdated, support for Exemplar is provided. Synopsys FPGA Express is not currently supported.</div> <bR> <div> <B> <A NAME="synplify"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>Synplify</B></div> <div> HDLmaker creates a Synplify project file when the -synplicity switch is used.</div> <bR> <div> hdlmaker -synplicity smartnic.top</div> <bR> <div> creates scripts/smartnic.prj</div> <bR> <div> set_option -technology VIRTEX</div> <div> set_option -part XCV300</div> <div> set_option -package BG352</div> <div> set_option -speed_grade -5</div> <div> add_file -constraint smartnic.sdc</div> <div> set_option -fanout_limit 100</div> <div> set_option -maxfan_hard false</div> <div> set_option -frequency 120</div> <div> set_option -symbolic_fsm_compiler 0</div> <div> set_option -resource_sharing 1</div> <div> set_option -pipe 1</div> <div> add_file -verilog "virtex.v"</div> <div> add_file -verilog "datapipe.v"</div> <div> add_file -verilog "dcache_ctrl.v"</div> <div> add_file -verilog "dcache_mux.v"</div> <div> add_file -verilog "mux2x64.v"</div> <div> add_file -verilog "ram16x18.v"</div> <div> add_file -verilog "srfifo_r2x_ctrl.v"</div> <div> add_file -verilog "srfifo_r2x.v"</div> <div> add_file -verilog "srfifo_r2x_12.v"</div> <div> add_file -verilog "srfifo_w2x_ctrl.v"</div> <div> add_file -verilog "srfifo_w2x.v"</div> <div> add_file -verilog "tmux3x64.v"</div> <div> add_file -verilog "zeroone.v"</div> <div> add_file -verilog "dcache.v"</div> <div> add_file -verilog "icache_ctrl.v"</div> <div> add_file -verilog "icache.v"</div> <div> add_file -verilog "inv.v"</div> <div> add_file -verilog "idelay16.v"</div> <div> add_file -verilog "inst_decode.v"</div> <div> add_file -verilog "irstbuff.v"</div> <div> add_file -verilog "mem_checker.v"</div> <div> add_file -verilog "command_queue.v"</div> <div> add_file -verilog "fifo_backoff.v"</div> <div> add_file -verilog "pci_arbitrator.v"</div> <div> add_file -verilog "pci_command_queue.v"</div> <div> add_file -verilog "pci_command_select.v"</div> <div> add_file -verilog "pci_flag_unit.v"</div> <div> add_file -verilog "pci_read_data_pipe.v"</div> <div> add_file -verilog "pci_sdram_control.v"</div> <div> add_file -verilog "pci_target_unit.v"</div> <div> add_file -verilog "pci_write_data_pipe.v"</div> <div> add_file -verilog "srfifo_ctrl.v"</div> <div> add_file -verilog "srfifo32.v"</div> <div> add_file -verilog "pci_interface.v"</div> <div> add_file -verilog "reg_file.v"</div> <div> add_file -verilog "sdram_interface.v"</div> <div> add_file -verilog "cmux2x1.v"</div> <div> add_file -verilog "shifter.v"</div> <div> add_file -verilog "smartnic_pads.v"</div> <div> add_file -verilog "timing.v"</div> <div> add_file -verilog "fifo_sp.v"</div> <div> add_file -verilog "xmac_receive_interface.v"</div> <div> add_file -verilog "xmac_receiver.v"</div> <div> add_file -verilog "xmac_transmit_interface.v"</div> <div> add_file -verilog "smartnic.v"</div> <bR> <div> A couple of helpful scripts are provided in HDLMAKER_LIB/csh. These are </div> <bR> <div> hdl_synplicity, runs hdlmaker and then copies all of the required files into the synplicity directory</div> <bR> <div> hdl_synplicity smartnic</div> <bR> <div> run_synplicity, invokes Synplify in batch mode,</div> <bR> <div> run_synplicity smartnic</div> <bR> <div> <B> <A NAME="synplicity_top_file_directives"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>Synplicity Directives</B></div> <div> There are several top file directives that are used to support Synplify. These are</div> <bR> <div> <A HREF="id22__maxfan.htm" TARGET="_top" TITLE="Top Files"><U>#maxfan</U></A></div> <div> <A HREF="id22__black_box.htm" TARGET="_top" TITLE="Top Files"><U>#black_box</U></A></div> <div> <A HREF="id22__synplicity.htm" TARGET="_top" TITLE="Top Files"><U>#synplicity</U></A></div> <div> <A HREF="id22__write_verilog_write_vhdl.htm" TARGET="_top" TITLE="Top Files"><U>#write_verilog</U></A></div> <div> <A HREF="id22__write_verilog_write_vhdl.htm" TARGET="_top" TITLE="Top Files"><U>#write_vhdl</U></A></div> <div> <A HREF="id22__resource_sharing_off.htm" TARGET="_top" TITLE="Top Files"><U>#resource_sharing_off</U></A></div> <div> <A HREF="id22__syn_directive.htm" TARGET="_top" TITLE="Top Files"><U>#syn_directive</U></A></div> <div> <A HREF="id22__pipe_off.htm" TARGET="_top" TITLE="Top Files"><U>#pipe_off</U></A></div> <bR> <bR> <div> <B> <A NAME="synopsys"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>Synopsys</B></div> <div> HDLmaker creates the required dcshell scripts and a Makefile for Synopsys. For each component of the design HDLmaker creates a dcshell script called foo.job. HDLmaker also creates a make file called design.Make. </div> <bR> <div> Here is a sample .job file</div> <bR> <div> TOP = fifo_sp</div> <div> PART = "xcv300bg352-5"</div> <div> company = "dataCentauri, Inc., Hudson, NH"</div> <bR> <div> read -format verilog fifo_sp.v</div> <bR> <div> uniquify</div> <bR> <div> current_design TOP</div> <div> remove_constraint -all</div> <bR> <div> compile -map_effort high</div> <bR> <div> report_fpga > fifo_sp.fpga</div> <bR> <div> report_timing > fifo_sp.timing</div> <bR> <div> write -format db -hierarchy -output fifo_sp.db</div> <div> exit</div> <bR> <div> Here is a sample Makefile</div> <bR> <div> smartnic.sedif: muxf5_32.db smartnic.db datapipe.db datapipe.db dcache.db dcache.db icache.db icache.db idelay16.db idelay16.db inst_decode.db inst_decode.db irstbuff.db irstbuff.db mem_checker.db mem_checker.db pci_interface.db pci_interface.db reg_file.db reg_file.db sdram_interface.db sdram_interface.db shifter.db shifter.db smartnic_pads.db smartnic_pads.db timing.db timing.db xmac_receiver.db xmac_receiver.db xmac_transmit_interface.db xmac_transmit_interface.db zeroone.db zeroone.db</div> <div>       dc_shell -f smartnic.job</div> <bR> <div> smartnic.db: smartnic.v datapipe.v datapipe.db dcache.v dcache.db icache.v icache.db idelay16.v idelay16.db inst_decode.v inst_decode.db irstbuff.v irstbuff.db mem_checker.v mem_checker.db pci_interface.v pci_interface.db reg_file.v reg_file.db sdram_interface.v sdram_interface.db shifter.v shifter.db smartnic_pads.v smartnic_pads.db timing.v timing.db xmac_receiver.v xmac_receiver.db xmac_transmit_interface.v xmac_transmit_interface.db zeroone.v zeroone.db</div> <div>       dc_shell -f smartnic.job</div> <bR> <bR> <div> datapipe.db: datapipe.v</div> <div>       dc_shell -f datapipe.job</div> <div> dcache.sedif: dcache.db dcache_ctrl.db dcache_ctrl.db dcache_mux.db dcache_mux.db mux2x64.db mux2x64.db ram16x18.db ram16x18.db srfifo_r2x.db srfifo_r2x.db srfifo_r2x_12.db srfifo_r2x_12.db srfifo_w2x.db srfifo_w2x.db tmux3x64.db tmux3x64.db zeroone.db zeroone.db</div> <div>       dc_shell -f dcache.job</div> <bR> <div> dcache.db: dcache.v dcache_ctrl.v dcache_ctrl.db dcache_mux.v dcache_mux.db mux2x64.v mux2x64.db ram16x18.v ram16x18.db srfifo_r2x.v srfifo_r2x.db srfifo_r2x_12.v srfifo_r2x_12.db srfifo_w2x.v srfifo_w2x.db tmux3x64.v tmux3x64.db zeroone.v zeroone.db</div> <div>       dc_shell -f dcache.job</div> <bR> <bR> <div> dcache_ctrl.db: dcache_ctrl.v</div> <div>       dc_shell -f dcache_ctrl.job</div> <bR> <div> dcache_mux.db: dcache_mux.v</div> <div>       dc_shell -f dcache_mux.job</div> <bR> <div> mux2x64.db: mux2x64.v</div> <div>       dc_shell -f mux2x64.job</div> <div> ram16x18.sedif: ram16x18.db</div> <div>       dc_shell -f ram16x18.job</div> <bR> <div> ram16x18.db: ram16x18.v</div> <div>       dc_shell -f ram16x18.job</div> <bR> <bR> <div> srfifo_r2x.sedif: srfifo_r2x.db srfifo_r2x_ctrl.db srfifo_r2x_ctrl.db</div> <div>       dc_shell -f srfifo_r2x.job</div> <bR> <div> srfifo_r2x.db: srfifo_r2x.v srfifo_r2x_ctrl.v srfifo_r2x_ctrl.db</div> <div>       dc_shell -f srfifo_r2x.job</div> <bR> <bR> <div> srfifo_r2x_ctrl.db: srfifo_r2x_ctrl.v</div> <div>       dc_shell -f srfifo_r2x_ctrl.job</div> <bR> <div> srfifo_r2x_12.sedif: srfifo_r2x_12.db srfifo_r2x_ctrl.db srfifo_r2x_ctrl.db</div> <div>       dc_shell -f srfifo_r2x_12.job</div> <bR> <div> srfifo_r2x_12.db: srfifo_r2x_12.v srfifo_r2x_ctrl.v srfifo_r2x_ctrl.db</div> <div>       dc_shell -f srfifo_r2x_12.job</div> <bR> <bR> <div> srfifo_w2x.sedif: srfifo_w2x.db srfifo_w2x_ctrl.db srfifo_w2x_ctrl.db</div> <div>       dc_shell -f srfifo_w2x.job</div> <bR> <div> srfifo_w2x.db: srfifo_w2x.v srfifo_w2x_ctrl.v srfifo_w2x_ctrl.db</div> <div>       dc_shell -f srfifo_w2x.job</div> <bR> <bR> <div> srfifo_w2x_ctrl.db: srfifo_w2x_ctrl.v</div> <div>       dc_shell -f srfifo_w2x_ctrl.job</div> <bR> <bR> <div> tmux3x64.db: tmux3x64.v</div> <div>       dc_shell -f tmux3x64.job</div> <bR> <div> zeroone.db: zeroone.v</div> <div>       dc_shell -f zeroone.job</div> <bR> <div> icache.sedif: icache.db icache_ctrl.db icache_ctrl.db ram16x18.db ram16x18.db</div> <div>       dc_shell -f icache.job</div> <bR> <div> icache.db: icache.v icache_ctrl.v icache_ctrl.db ram16x18.v ram16x18.db</div> <div>       dc_shell -f icache.job</div> <bR> <bR> <div> icache_ctrl.db: icache_ctrl.v</div> <div>       dc_shell -f icache_ctrl.job</div> <div> ram16x18.sedif: ram16x18.db</div> <div>       dc_shell -f ram16x18.job</div> <bR> <div> ram16x18.db: ram16x18.v</div> <div>       dc_shell -f ram16x18.job</div> <bR> <bR> <bR> <div> idelay16.sedif: idelay16.db inv.db inv.db zeroone.db zeroone.db</div> <div>       dc_shell -f idelay16.job</div> <bR> <div> idelay16.db: idelay16.v inv.v inv.db zeroone.v zeroone.db</div> <div>       dc_shell -f idelay16.job</div> <bR> <bR> <div> inv.db: inv.v</div> <div>       dc_shell -f inv.job</div> <bR> <div> zeroone.db: zeroone.v</div> <div>       dc_shell -f zeroone.job</div> <bR> <bR> <div> inst_decode.db: inst_decode.v</div> <div>       dc_shell -f inst_decode.job</div> <bR> <div> irstbuff.db: irstbuff.v</div> <div>       dc_shell -f irstbuff.job</div> <bR> <div> mem_checker.db: mem_checker.v</div> <div>       dc_shell -f mem_checker.job</div> <div> pci_interface.sedif: pci_interface.db command_queue.db command_queue.db command_queue.db command_queue.db fifo_backoff.db fifo_backoff.db pci_arbitrator.db pci_arbitrator.db pci_command_queue.db pci_command_queue.db pci_command_select.db pci_command_select.db pci_flag_unit.db pci_flag_unit.db pci_read_data_pipe.db pci_read_data_pipe.db pci_sdram_control.db pci_sdram_control.db pci_target_unit.db pci_target_unit.db pci_write_data_pipe.db pci_write_data_pipe.db srfifo32.db srfifo32.db zeroone.db zeroone.db</div> <div>       dc_shell -f pci_interface.job</div> <bR> <div> pci_interface.db: pci_interface.v command_queue.v command_queue.db command_queue.v command_queue.db fifo_backoff.v fifo_backoff.db pci_arbitrator.v pci_arbitrator.db pci_command_queue.v pci_command_queue.db pci_command_select.v pci_command_select.db pci_flag_unit.v pci_flag_unit.db pci_read_data_pipe.v pci_read_data_pipe.db pci_sdram_control.v pci_sdram_control.db pci_target_unit.v pci_target_unit.db pci_write_data_pipe.v pci_write_data_pipe.db srfifo32.v srfifo32.db zeroone.v zeroone.db</div> <div>       dc_shell -f pci_interface.job</div> <bR> <bR> <div> command_queue.db: command_queue.v</div> <div>       dc_shell -f command_queue.job</div> <bR> <div> fifo_backoff.db: fifo_backoff.v</div> <div>       dc_shell -f fifo_backoff.job</div> <bR> <div> pci_arbitrator.db: pci_arbitrator.v</div> <div>       dc_shell -f pci_arbitrator.job</div> <bR> <div> pci_command_queue.db: pci_command_queue.v</div> <div>       dc_shell -f pci_command_queue.job</div> <bR> <div> pci_command_select.db: pci_command_select.v</div> <div>       dc_shell -f pci_command_select.job</div> <bR> <div> pci_flag_unit.db: pci_flag_unit.v</div> <div>       dc_shell -f pci_flag_unit.job</div> <bR> <div> pci_read_data_pipe.db: pci_read_data_pipe.v</div> <div>       dc_shell -f pci_read_data_pipe.job</div> <bR> <div> pci_sdram_control.db: pci_sdram_control.v</div> <div>       dc_shell -f pci_sdram_control.job</div> <bR> <div> pci_target_unit.db: pci_target_unit.v</div> <div>       dc_shell -f pci_target_unit.job</div> <bR> <div> pci_write_data_pipe.db: pci_write_data_pipe.v</div> <div>       dc_shell -f pci_write_data_pipe.job</div> <div> srfifo32.sedif: srfifo32.db srfifo_ctrl.db srfifo_ctrl.db</div> <div>       dc_shell -f srfifo32.job</div> <bR> <div> srfifo32.db: srfifo32.v srfifo_ctrl.v srfifo_ctrl.db</div> <div>       dc_shell -f srfifo32.job</div> <bR> <bR> <div> srfifo_ctrl.db: srfifo_ctrl.v</div> <div>       dc_shell -f srfifo_ctrl.job</div> <bR> <bR> <div> zeroone.db: zeroone.v</div> <div>       dc_shell -f zeroone.job</div> <bR> <bR> <div> reg_file.db: reg_file.v</div> <div>       dc_shell -f reg_file.job</div> <bR> <div> sdram_interface.db: sdram_interface.v</div> <div>       dc_shell -f sdram_interface.job</div> <div> shifter.sedif: shifter.db cmux2x1.db cmux2x1.db</div> <div>       dc_shell -f shifter.job</div> <bR> <div> shifter.db: shifter.v cmux2x1.v cmux2x1.db</div> <div>       dc_shell -f shifter.job</div> <bR> <bR> <div> cmux2x1.db: cmux2x1.v</div> <div>       dc_shell -f cmux2x1.job</div> <bR> <bR> <div> smartnic_pads.db: smartnic_pads.v</div> <div>       dc_shell -f smartnic_pads.job</div> <bR> <div> timing.db: timing.v</div> <div>       dc_shell -f timing.job</div> <div> xmac_receiver.sedif: xmac_receiver.db fifo_sp.db fifo_sp.db xmac_receive_interface.db xmac_receive_interface.db</div> <div>       dc_shell -f xmac_receiver.job</div> <bR> <div> xmac_receiver.db: xmac_receiver.v fifo_sp.v fifo_sp.db xmac_receive_interface.v xmac_receive_interface.db</div> <div>       dc_shell -f xmac_receiver.job</div> <bR> <bR> <div> fifo_sp.db: fifo_sp.v</div> <div>       dc_shell -f fifo_sp.job</div> <bR> <div> xmac_receive_interface.db: xmac_receive_interface.v</div> <div>       dc_shell -f xmac_receive_interface.job</div> <bR> <bR> <div> xmac_transmit_interface.db: xmac_transmit_interface.v</div> <div>       dc_shell -f xmac_transmit_interface.job</div> <bR> <div> zeroone.db: zeroone.v</div> <div>       dc_shell -f zeroone.job</div> <bR> <div> muxf5_32.db: muxf5_32.v</div> <div>       dc_shell -f muxf5_32.job </div> <bR> <bR> <div> <B> <A NAME="synopsys_directives"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>Synopsys Directives</B></div> <div> There are several top file directives which support Synopsys. These are,</div> <bR> <div> <A HREF="id22__dont_touch.htm" TARGET="_top" TITLE="Top Files"><U>#dont_touch</U></A></div> <div> <A HREF="id22__flatten.htm" TARGET="_top" TITLE="Top Files"><U>#flatten</U></A></div> <div> <A HREF="id22__synopsys.htm" TARGET="_top" TITLE="Top Files"><U>#synopsys</U></A></div> <div> <A HREF="id22__boundary_optimization.htm" TARGET="_top" TITLE="Top Files"><U>#boundary_optimization</U></A></div> <bR> <div> <B> <A NAME="common_directives"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>Common Directives</B></div> <div> These directives are used with both Synplify, Synopsys as well as the Xilinx place and route tools.</div> <div> <A HREF="id22__clock.htm" TARGET="_top" TITLE="Top Files"><U>#clock</U></A></div> <bR> <div> <B> <A NAME="precision"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>Precision</B></div> <div> HDLmaker creates a Mentor Precision project file (.psp) when the -precision switch is used.</div> <bR> <bR> <bR> <bR> </td> </tr></table></body>