pin_file_format
*********************.pin file format ***************************
Pin files define both top level and sub module IO. At the top level of a design the
pin file is used to generate a pad ring. It also defines the pin locations, strength,
type, speed, setup time, hold times, logic levels, and timing constraints. For the lower
levels of a design the pin file is used to define the module's pin names.
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The following is an example of a sub module pin file. The keyword #nopadring is used to
tell hdlmaker not to generate a padring.
#nopadring
#pins
fb_data[487:0] type = in;
sysclk type = in;
gblreset type = in;
tclk type = in;
scan_enb type = in;
scan_in type = in;
scan_out type = out;
mclock[15:5] type = in;
cmd_op[31:0] type = in;
chip[15:0] type = in;
done type = out;
data[487:0] type = out;
enb_data_l[471:0] type = out;
enb_external_io_l[15:0] type = out;
cntr[26:0] type = out;
enb_special_l[5:0] type = out;
special[5:0] type = out;
fb_special[5:0] type = in;
enb_special_l[5:0] type = out;
#endpins
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The following is an example of a top level pin file. The keyword #uselibrary tells
hdlmaker to directly instantiate the IO components. If the #uselibrary keyword is
left off then hdlmaker will generate Verilog or VHDL code for the pad ring. For supported
FPGAs, #uselibrary is the prefered method. For unsupported FPGAs and for ASICs the
Verilog/VHDL code method will work.
#uselibrary
#pins
scan_tms type = in,clk=tclk,pin = at10;
scan_tdo type = out,c2p=7,pin = at8;
scan_tdi type = in,p2s=7,pin = at7;
tclkin type = clkp,pin = aw19;
tclk type = internal;
mclock[15:5] type = in,clk=sysclk,pin = [v35,u35,ac35,ab35,ar23,ar22,ar18,ac5,ab5,u5,v5];
vclock type = clkp,pin = d21;
clkreset type = in,pin = [e22];
reset type = in,pin=e23;
sysclk type = internal;
z_vwires_r[43:0] type = inout,resistor=pullup,clk=sysclk,triclk=sysclk,tristate=enb_z_vwires_r_l[43:0],pin = [ar36,f4,at6,d34,an36,j4,at9,d31,ak36,n4,at14,d27,af36,u4,at17,d25,ac36,aa4,at19,d23,aa36,ac4,at22,d19,w36,ae4,at24,d16,t36,ag4,at27,d13,n36,ak4,at30,d10,j36,am4,at32,d8,f36,ap4,at34,d6];
enb_z_vwires_r_l[43:0] type = internal;
vclock type = clkp,pin = d21;
#endpins
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#title (optional) Specifies the entity name when the .pin file is processed alone.
If the .pin file is called from a .top file then the title is taken from the #module statement
in the .top file (if present) or from the top file's name if no #module statement is present.
If there the pin file is processed alone and there is no #title statement then the pin file's
name is used, i.e. if the pin file is called foo.pin then the resulting file will be foo_pads.v
or foo_pads.vhd.
#title "file_name"
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#revision
The #revision statement is optional. It is used for the RCS revision header.
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#uselibrary
#uselibrary is for padrings. It causes hdlmaker to use
Xilinx IO cells directly instead of writing pure Verilog or VHDL.
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#nopadring
#nopadring is for internal components that do not require pad rings.
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#tristate_prefix,#prefix,#postfix
Unless #nopadring is specified, Hdlmaker generates module/entity pin names of the form
'prefix'_name_'postfix for inputs and outputs
'tristate_prefix'_name_'postfix for inouts
The defaults are
prefix ""
postfix "pin"
tristate_prefix "t_"
Thus for the signal input foo, and inout bar, the external pin name will be
foo_pin if foo is an input or output
t_bar_pin if foo is an input.
The tristate_prefix, prefix and postfix may be overridden with the #tristate_prefix, #prefix and #postfix
statements.
Example:
#tristate_prefix "tri_";
#prefix "pad_";
#postfix "";
would generate
pad_foo
tri_pad_bar
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Signal name formats:
The legal characters for signal names are a-z,0-9 and _. If the signal refers to a bus or
bus fragment then the format is signal_name[#] or signal_name[#..#] where .. represents a
range. Examples of legal names are
foo
foo_bar[3]
myname[8..15]
yourname[31..0]
The following name is illegal because the name portion of the string contains a number.
name12[15..19]
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Default signal names.
For bidirectional IOs hdlmaker has the following conventions
name Internal source name
fb_name Feedback signal from the IO pin
name_pin Name of pin.
For all unidirectional pins
name Internal signal name
name_pin Pin name
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Type field:
The type field specifies the direction of the pin. The available types are
in input
out output
inout bidirectional or tristate
rsvd reserved (used to preserve a pin number for future use)
clks Xilinx secondary clock buffer
clkp Xilinx primary clock buffer
tdo Xilinx 4000 tdo buffer (for 5200 or ORCA use a regular out)
internal Internal control signal (for example clock enables or tristate enables)
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clk,inclk,outclk,lch,triclk:
The clk statement specfies the clk to the IO registers.
clk=sysclk positive edge triggered clock
clk=!sysclk negative edge triggered clock
lch=sysclk High true latch enable (inputs only)
lch=!sysclk Low true latch enable(inputs only)
inclk=sysclk positive edge triggered input clock
inclk=!sysclk negative edge triggered input clock
outclk=sysclk positive edge triggered output clock
outclk=!sysclk negative edge triggered output clock
triclk=sysclk positive edge triggered tristate enable reg
triclk=!sysclk negative edge triggered tristate enable reg
If no clk statement is present then the IO pin is assumed to be combinatorial
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inclkenb,outclkenb,ioclkenb,triclkenb:
Input and output clock enables are specified as follows:
inclkenb=enb_name Input flipflop enable
outclkenb=enb_name Output enable
inoutenb=enb_name Both
Tristate enable register clock enable is specified as follows:
triclkenb = enb_name
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enable:
The tristate buffer enable, high = enable, low = disable(tristate). The enable statement has the form:
enable=!enb_l Enable the output of enable is low
enable=enb Enable the output if enable_l is high
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tristate:
The tristate buffer disable, high = disable, low = enable. The tristate statement has the form:
tristate=!enb Enable the output of enb is high
tristate=enb_l Enable the output if enb_l is low
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triresetlevel:
The default tristate enable register reset level is 1. If a clear is desired then use
triresetlevel=0
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resetlevel:
The default reset level is 0. If a preset is desired then use
resetlevel=1
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resistor:
Pullup and pulldown resistors ,may be specified as follows:
resistor=pullup
resistor=pulldown
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speed,setup:
The speed of the outputs and hold time characteristics of the inputs may be controled as follows:
speed=slow Use the slew limited output buffers, default is the fast buffers
speed=fast Use the fast output buffers, default is the fast buffers
setup=nodelay Use the fast input buffers, some hold time will be required.
setup=nohold Use the slow input buffers, hold time is 0, setup time is much longer
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p2s,c2p:
Xilinx timing constraints.
p2s=16 The pin to setup time of this pin is 16 ns.
c2p=20 The clock to pin time of this pin is 20 ns.
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alias:
The alias statement is used to provide an additional connection to a pin. Xilinx inputs can
be both registered and combinatorial at the same time. An example is shown below:
txbusy type = in,clk = sysclk,pin=128,resetlevel=1;
nxttxbusy type = in,alias = txbusy,p2s=16 ;
txbusy is registered,nxttxbusy is combinatorial.
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pin:
The pin statement specifies the pin numbers. The pin list is an arbitrary list of numbers.
Examples:
pin=12
pin=[0..3,8,31..20,7]
ranges can be either high to low or low to high and can be mixed in a single list. The pin
numbers are matched to the bus pins from left to right.
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strength:
The strength statement specified the drive strength of the output buffer. For Virtex the valid values are 2,4,6,8,12,16 & 24.
strength=24
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logic:
The logic statement specifies the logic levels. The default is logic family is LVTTL. The strength, fast and slow statements should only be used in conjunction with the default LVTTL levels.
The valid logic levels for Virtex are:
logic=GTL
logic=GTLP
logic=HSTL_I
logic=HSTL_III
logic=HSTL_IV
logic=LVCMOS2
logic=PCI33_3
logic=PCI33_5
logic=PCI66_3
logic=SSTL2_I
logic=SSTL2_II
logic=SSTL3_I
logic=SSTL3_II