running_hdlmaker
hdlmaker [-simulate][-gblreset][-noreset] filename.xxx filename.xxx ...
File extensions:
.abl Abel file
.cvrt Convert a list of text files to the specified format (default UNIX)
.pin A pin list used to generate a Xilinx pad ring
.pnl or .sl A PadsPCB file (requires a .ref file also)
.top A top level file which connects a series of components
.vhd VHDL file
.v Verilog file
.net Hdlmaker netlist format. Produced automatically when the -cnet,-pnet,-schematic,or -pads switches
are applied to a .top file i.e.
hdlmaker -pads foo.top
.cnet Scald netlist format
.alg Contains a part substitution list for a .cnet file, also used for back annotation when the
-backannotate switch is used. .alg files have the form
#part u10 foo.top foo.pin;
#part r5 resistor.v;
#part r12 resister_330.top foo.pin;
The pin file name is optional when the .alg file is used only for part substitution,
it is required for back annotation.
Switches:
-simulate Generates special code for simulation (default synthesis code)
-gblreset Add an async reset (called gblreset) to all registers and latches
-noreset Never add an async reset
If neither gblreset or noreset is set then hdlmaker adds gblreset to all registers in
any abel file that doesn't have a device field
-unix All generated files are in Unix format (default)
-dos All generated files are in DOS format
-mac All generated files are in Macintosh format
-part_type xxx Overrides the parttype in the top file
-family xxx Overrides the family in the top file
-package xxx Overrides the package in the top file
-speed xxx Overrides the speed in the top file
-update Update the local copies of the library components
-library xxx Specifies the selected directory as the primary library
-xnf Force Synopsys to write out a SXNF file
-edif Force Synopsys to write out a SEDIF file
The defaults are SXNF format for Xilinx and SEDIF of Lucent
-batchq xxx Specify the Batch Queue script name to be called by the Make files
-html Generate hyperlinked, syntax colored HTML files. Works on any kind of source
file.
-autopin Automatically pins the part. Pins are assigned to sequential pads.
Only unassigned pins are effected.
-repin Completely re-pins the part.
-reverse Reverse the order in which autopin and repin assign pins
Default orders is foo[7:0] will be assigned from 7 to 0
Reverse assigns from 0 to 7
-stripp Strip off the leading Ps in pin numbers
-stimulus Makes an empty stimulus file. The pins on the entity are a mirror image
of the pins in the .pin file (for top files) or the pins on the connector
for a pc board.
-synopsys Overrides the HDLMAKER_SYNTHESYS env variable to force the generation
of Synopsys compatible vhdl files (most importantly the pad ring file);
-synplicity Overrides the HDLMAKER_SYNTHESYS env variable to force the generation
of Synplicity compatible vhdl files (most importantly the pad ring file);
-fpgaexpress Overrides the HDLMAKER_SYNTHESYS env variable to force the generation
of FPGAexpress compatible vhdl files (most importantly the pad ring file);
-exemplar Overrides the HDLMAKER_SYNTHESYS env variable to force the generation
of Exemplar compatible vhdl files (most importantly the pad ring file);
-rtlc Overrides the HDLMAKER_SYNTHESYS env variable to force hdlmaker to generate
RTLC scripts
-verilog Overrides the HDLMAKER_LANGUAGE env variable to force hdlmaker to generate
verilog.
-vhdl Overrides the HDLMAKER_LANGUAGE env variable to force hdlmaker to generate
VHDL.
-leapfrog Overrides the HDLMAKER_SIMULATOR env variable to force hdlmaker to generate
Leapfrog scripts and Makefiles
-verilogxl Overrides the HDLMAKER_SIMULATOR env variable to force hdlmaker to generate
VerilogXL scripts
-modeltech Overrides the HDLMAKER_SIMULATOR env variable to force hdlmaker to generate
Model technology scripts
-map_effort Overrides the HDLMAKER_SYNOPSYS_MAP_EFFORT env variable, sets the Synopsys map_effort level
-upcase_io Overrides the HDLMAKER_UPCASE_IO env variable, If 1 the IO component names will be upcased
for synthesys (but not for simulation). Upcase_io is used for Verilog, ignored for VHDL
-caps Include capacitors when converting to or from PC board netlists
-nocaps Exclude capacitors when converting to or from PC board netlists (default)
-cnet Generate a Scald Concise netlist (.cnet file)
des_inta_l r44 2 sresistor_1k
des_inta_l u1 11 pci_speed_bump
-pnet Generate a .pnet file. Entries have the form
u1.2 des_clk000
u1.3 des_req_l
u1.4 des_gnt_l
-includeio Add the pin IO type to the .pnet file
u1.2 des_clk000 clkp
u1.3 des_req_l in
u1.4 des_gnt_l out
u1.5 des_rst_l out
-pads Generate a Pads PCB netlist (.asc file). Entries have the form
*SIGNAL* R_DES_AD030 12.00 0 0 0 -2
J7.45 S7.2
-newnet Convert a .cnet file into a full .net file, also works with a .alg file
-board Include the non-IO pins on the entity or module generated from a .pin file. I.E.
include grounds,power,jtag, initialization ..., Use the -board switch when building'
pc boards, don't use it when building an FPGA. A #part_type "board" has the same
effect.
-makeinclude Convert a .net file into a c include file
-schematic Make a TCL schematic. Run a TCL app like WISH to view the schematics and to
produce postscript versions.
-width Page width of the schematic in .1 inch increments, for example 8.5 inches is 85
HDLMAKER_PAGE_WIDTH env variable defines the default
-height Page height of the schmatic in .1 inch increments
HDLMAKER_PAGE_HEIGHT env variable defines the default
-rotate Schematic orientation, 0 = portrait, 1 = landscape
HDLMAKER_PAGE_ROTATE env variable defines the default
-placevertical Place the components on the schematic page from top to bottom instead of from left to right
-limitbus Limits the size of buses when converting from cnet to verilog. Buses are broken up into ten
bit chunks
-pcf Generate a Xilinx pcf file
-partition Generate a partition report (.cnct) which can be used to partition design into two packages.
The partition report orders the components via two different algorithms, one which seeks to
reduce the number of interconnects between the two groups, and one which maximizes the connectivity
within each group. In addition, when used in conjuction with the Synopsys FPGA compiler,in
lists the percentage of the total number of CLBs used at each partion cut.
-makepinfile Generate a .pin file for every vhdl or verilog component that doesn't have one.
-makepinfromnet Extract the pin files from a .cnet netlist. These pin files can be used to create models
of the components in a netlist or as back annotation files,
hdlmaker -makepinfromnet foo.cnet
-buffer out_type Specify the VHDL output type (default is buffer).
-buffer out
-buffer inout
-casesensitive Do not downcase code (Use for verilog only). Allow the use of uppercase characters in file names and
Verilog module and signal names.
-backannotate Back annotate the .pin files in a design. The -backannotate switch is used in conjunction with
a .alg file (which can be generated for the original design by using the -cnet switch) which
lists the components and their respective .pin files. Hdlmaker will copy the old pin files to
the ./bak directory and then update the .pin files from the corresponding backannotation file
which has the name of the form u#.pin. The backannotation files can be generated from a .cnet
file with the -makepinfromnet switch.
hdlmaker -backannotate foo.alg
To do a complete backannotation for a netlist do the following
hdlmaker -makepinfromnet foo_updated.cnet
hdlmaker -backannotate foo.alg
A script is provided to do the whole backannotation job.
hdl_backanno old_name new_name
where old_name is the pre-layout name, and new_name is the name of the post-layout .cnet
netlist. For example
hdl_backanno foo foo_pcb
will backannotate the pin files and generate a model called foo_pcb.v or foo_pcb.vhd. It's
best to use a new directory for this, using a polybus.lib file of a -library switch to point
back to the source directory.
Examples:
hdlmaker foo.abl
hdlmaker foo.abl bar.abl
hdlmaker -simulate foo.top
hdlmaker -mac foo.cvrt
hdlmaker -part_type xc4013e -speed 3 -package pq240 foo.top
hdlmaker -batchq S3fpga2job_q foo.top
hdlmaker -upcase_io 1 foo.top
hdlmaker -buffer out foo.top
note: All filenames must be lowercase
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polybus.lib Search path file
The polybus.lib file contains a search path list for Hdlmaker. The directories are searched
in order starting with the local directory, followed by the directories in polybus.lib, and
then the hdlmaker standard libraries.
Example polybus.lib file
#define "my_lib_a" "/tmp_mnt/ma/lincoln/u/polybus/vhdl_sources/xc4013/my_lib_a"
#define "my_lib_b" "/tmp_mnt/ma/lincoln/u/polybus/vhdl_sources/xc4013/my_lib_b"
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Scripts (Found in $HDLMAKER_LIB/csh)
hdl_cleanup Creates all of the required subdirectories and moves all of the
files in to the appropriate subdirectories
hdl_synopsys $1 Creates a directory for Synopsys and copies all of the appropriate
files into it. The argument specifies that top level design name (no extension)
hdl_synplicity $1 Creates a directory for Synplicity and copies all of the appropriate
files into it. The argument specifies that top level design name (no extension)
hdl_exemplar $1 Creates a directory for Exemplar and copies all of the appropriate
files into it. The argument specifies that top level design name (no extension)
hdl_leapfrog $1 Creates a directory for Leapfrog and copies all of the appropriate
files into it. The argument specifies that top level design name (no extension)
hdl_verilogxl $1 Creates a directory for Verilogxl and copies all of the appropriate
files into it. The argument specifies that top level design name (no extension)
hdl_modeltech $1 Creates a directory for Modeltech and copies all of the appropriate
files into it. The argument specifies that top level design name (no extension)
tarbaby $1 Tars and compresses and uu-encodes the directory specified by the argument
untarbaby $1 Uncompresses and untars a .tar.Z file
hdl_backanno $1 $2 Back annotate the pin files and generate a new model. $1 is the original design,
$2 is the new post layout design