TOP = sample_pads
PART = "4013EPQ240-3"
read -format vhdl sample_pads.vhd

uniquify

current_design TOP
remove_constraint -all
dont_touch "mclk_01_i"
dont_touch "mclk_08_i"
dont_touch "mclk_09_i"
dont_touch "probe_00_o"
dont_touch "probe_01_o"
dont_touch "sysclk_i"


compile -map_effort high

report_fpga > sample_pads.fpga

report_timing > sample_pads.timing

write -format db -hierarchy -output sample_pads.db
exit