HDLmaker is offered free of charge by Polybus Systems corporation under a BSD style open source license.
Polybus offers Intellectual Property including InfiniBand Link Layer and Transport Layer cores, and a comprehensive set of In System FPGA test patterns. Polybus also provides FPGA and ASIC design services.
Polybus is the leading supplier of InfiniBand cores for use in Xilinx Virtex2P, Xilinx Virtex4FX, Xilinx Virtex5, Xilinx Virtex6, Altera Stratix2GX and Stratix4GX and GT FPGAs as well for ASICs. We offer an IBA Release 1.1 compliant Link Layer core (10GBit/Second), an IBA Release 1.2 compatible Double Data Rate Link Layer core (20GBit/Second) , a 4X QDR Link Layer Core (40GBits/Second) for the Stratix4GT and the Virtex6HXT and an 8X QDR Link Layer Core (80 Gbits/Second) of ASICs. SDR and DDR InfiniBand Target Channel Adapters are available for both Altera and Xilinx FPGAs. For more information see,
If you are looking for FPGA or ASIC design consulting or would like more information about our cores please contact Joshua Rosen firstname.lastname@example.org, (978) 828-0944.
HDLmaker may be downloaded here.
HDLmaker is a tool for generating Verilog designs. HDLmaker simplifies the development of complex FPGA designs as well as PC Boards by performing the following tasks:
Writes hierarchical Verilog code
Generates retargetable IO pad rings
Generates all of the necessary scripts and Make files
Supports mulitlanguage projects
Designs are portable between FPGA families and CAE tools
Simplifies the reuse of HDL code
Converts HDLmaker, Verilog and VHDL files into fully hyper linked HTML
The designer writes the leaf cells and defines the pins, HDLmaker does the rest.
HDLmaker is an open source program that runs on any Linux/UNIX. HDLmaker has been tested on Sun OS, Solaris, HP, Linux and SGI systems.
HDLmaker also runs under the Cygwin environment on Windows. Cygwin is available from http://www.cygwin.com
Writes Hierarchical Verilog.
Output can be targeted to either Verilog or VHDL (VHDL support has been deprecated).
Supports mixed language development.
Generates PC board netlists in both PADS PCB and SCALD formats.
Generates Schematics in Postscript format.
Supports the most popular FPGAs
Xilinx Virtex6,Virtex5,Virtex4,Virtex2P, Virtex2,VirtexE,Virtex, Spartan3, Spartan2,4000E,4000EX,4000XL,5200,9500, Altera Stratix ,Stratix2GX,Stratix4GX,Stratix4GT
Supports the most popular synthesizers
Synopsys Design Compiler
Supports most simulators
Cadence Verilog XL
Mentor Questa and ModelSim
HDLmaker generates an HTML version of the design with hyper links from all source files to generated files and from all component instances to the component's module. Verilog and VHDL HTMLized are also syntax colored.
HDLmaker based designs can be easily retargeted to different FPGA or ASIC families, tools and languages, usually with a simple command line switch or with a single line in a source file.
Any supported synthesizer or simulator can be used without any additional work on the part of the user.
HDLmaker may be used by individuals and corporations for the design and development of FPGAs and ASICs at no charge. HDLMaker is available under a BSD style license
Added #code, #parameter
Added Virtex5 support
Added more support for Stratix2 and Stratix2GX
Added support for Virtex2ProX, Spartan3e and Stratix2GX
Creates Makefiles for ModelSim
More Virtex4 support
Added frczero to the .pin file
insert_compare, Inserts a module with a compare wrapper around it
Added HDLMAKER_ALLOW_SUB variable
Floorplanning support for Multipliers and Block RAMs
New XST constraints
Improved DDR IO support including differential DDR
Improved Xilinx project support
Better ModelSim support. Creates three command files, foo_compile_mt.cmd to compile the modules, foo_i_mt.cmd for interactive use, and foo_batch_mt.cmd for batch simulation.
Initial values of HDLmaker variables can be passed in from the command line or from a file
Better comment support
More flexible #clock statement
Comments in pin files
Support for Xilinx ISE 6.1
Support for Virtex2P
Support for Precision and ModelSim added
Large Project Support, HDLMaker now operates across multiple directories
Virtex2, Spartan2 and Spartan2E support added
Altera Stratix support added
Multilanguage project support. Can embed VHDL entities into Verilog files and Verilog modules into VHDL files
Altera Stratix4GX and GT
Support for Quartus II 9.1 and ISE 11
Support for Acronix Speedster FPGAs
Support for Verilog 2001 port definitions
Added -tree_copy and -src_copy switches which generate export scripts
Services (Not free)
FPGA and ASIC design
An IBA Release 1.1 compliant 4X/1X InfiniBand Link Layer Core and a companion Transport Layer Core. The Link Layer Core operates at 4X speeds with minimal latency and is suitable for use in both Xilinx Virtex 2P FPGAs and ASICs. A highly customizable companion Transport Layer Core is also available which is suitably for a range of Target Channel Applications.
A customizable set of FPGA test patterns for all Xilinx FPGAs. The suite consists of over 400 patterns which test the internal functionality and interconnect of any Xilinx FPGA. The tests help eliminate FPGAs that have failed due to handling problems and infant mortality. In addition the patterns provided a greatly enhanced level of testing which helps assure the future upgradability of FPGA based systems.
Customization (Not Free)
Polybus will customize HDLmaker for your environment: Add conversions between any netlist format and either VHDL or Verilog including any custom attributes that are specific to your company.
Add support for other simulators and synthesis tools
Provide glue between different CAE tools.