Pin Files

<body topmargin=0 leftmargin=0 marginheight=0 marginwidth=0> <table cellpadding=0 cellspacing=0 border=0><tr> <td valign="top" colspan=2 height=90 BGCOLOR="#CC9900" TEXT="#080000" bgproperties="fixed" background="045005a0dwnjzk.gif"> <div> <A HREF="index.htm" TARGET="_top" TITLE="HDLmaker"><U><B>home</B></U></A><B>     | </B><B> </B><B> </B><B>  </B><FONT SIZE="5" COLOR="#FFCC66" FACE="Arial" ><B>HDLmaker</B></FONT></div> <div> <A HREF="id22.htm" TARGET="_top" TITLE="Top Files"><U><B>Top Files</B></U></A><B>   |   </B><B>Pin Files</B><B>   |   </B><A HREF="id24.htm" TARGET="_top" TITLE="Language"><U><B>Language</B></U></A><B>   |   </B><A HREF="id28.htm" TARGET="_top" TITLE="Directory Organization"><U><B>Directory Organization</B></U></A><B>   |   </B><A HREF="id29.htm" TARGET="_top" TITLE="Simulation"><U><B>Simulation</B></U></A><B>   |   </B><A HREF="id30.htm" TARGET="_top" TITLE="Synthesis"><U><B>Synthesis</B></U></A><B>   |   </B><A HREF="id33.htm" TARGET="_top" TITLE="Xilinx Tools"><U><B>Xilinx Tools</B></U></A><B>   |   </B><A HREF="id25.htm" TARGET="_top" TITLE="Examples"><U><B>Examples</B></U></A></div> <div> </div> </td> </tr><tr> <td valign="top" width=210 BGCOLOR="#FFFFFF" TEXT="#080000"> <div> Pin Files</div> <div> <B><IMG SRC="05a69830.gif" border=0 width="105" height="131" ALIGN="BOTTOM" HSPACE="0" VSPACE="0"></B><A HREF="http://www.polybus.com" TARGET="_top" TITLE="http://www.polybus.com"><U><B>Polybus</B></U></A></div> <bR> <div> <A HREF="id23_m.htm#basic_pin_file_format" TARGET="TRLX_Middle" TITLE="Pin Files"><U><B>Basic Pin File Format</B></U></A></div> <div> <A HREF="id23_m.htm#top_level_pin_file_format" TARGET="TRLX_Middle" TITLE="Pin Files"><U><B>Top Level Pin File Format</B></U></A></div> <bR> <div> <A HREF="id23_m.htm#_uselibrary" TARGET="TRLX_Middle" TITLE="Pin Files"><U><B>#uselibrary</B></U></A></div> <div> <A HREF="id23_m.htm#_nopadring" TARGET="TRLX_Middle" TITLE="Pin Files"><U><B>#nopadring</B></U></A></div> <div> <A HREF="id23_m.htm#_frczero" TARGET="TRLX_Middle" TITLE="Pin Files"><U><B>#frczero</B></U></A></div> <div> <B>#tristate_prefix,#prefix,#postfix</B></div> <div> <A HREF="id23_m.htm#signal_name_formats" TARGET="TRLX_Middle" TITLE="Pin Files"><U><B>Signal name formats</B></U></A></div> <div> <A HREF="id23_m.htm#default_signal_names_" TARGET="TRLX_Middle" TITLE="Pin Files"><U><B>Default signal names</B></U></A></div> <div> <A HREF="id23_m.htm#type_field" TARGET="TRLX_Middle" TITLE="Pin Files"><U><B>Type field</B></U></A></div> <div> <B>clk,inclk,outclk,lch,triclk</B></div> <div> <A HREF="id23_m.htm#inclkenboutclkenbioclkenbtriclkenb" TARGET="TRLX_Middle" TITLE="Pin Files"><U><B>inclkenb,outclkenb,ioclkenb,triclkenb</B></U></A></div> <div> <A HREF="id23_m.htm#enable" TARGET="TRLX_Middle" TITLE="Pin Files"><U><B>enable</B></U></A></div> <div> <A HREF="id23_m.htm#tristate" TARGET="TRLX_Middle" TITLE="Pin Files"><U><B>tristate</B></U></A></div> <div> <A HREF="id23_m.htm#triresetlevel" TARGET="TRLX_Middle" TITLE="Pin Files"><U><B>triresetlevel</B></U></A></div> <div> <A HREF="id23_m.htm#resetlevel" TARGET="TRLX_Middle" TITLE="Pin Files"><U><B>resetlevel</B></U></A></div> <div> <A HREF="id23_m.htm#resistor" TARGET="TRLX_Middle" TITLE="Pin Files"><U><B>resistor</B></U></A></div> <div> <A HREF="id23_m.htm#p2sc2p" TARGET="TRLX_Middle" TITLE="Pin Files"><U><B>p2s,c2p</B></U></A></div> <div> <A HREF="id23_m.htm#alias" TARGET="TRLX_Middle" TITLE="Pin Files"><U><B>alias</B></U></A></div> <div> <A HREF="id23_m.htm#pin" TARGET="TRLX_Middle" TITLE="Pin Files"><U><B>pin</B></U></A></div> <div> <A HREF="id23_m.htm#strength" TARGET="TRLX_Middle" TITLE="Pin Files"><U><B>strength</B></U></A></div> <div> <A HREF="id23_m.htm#logic" TARGET="TRLX_Middle" TITLE="Pin Files"><U><B>logic</B></U></A></div> <div> <A HREF="id23_m.htm#comment" TARGET="TRLX_Middle" TITLE="Pin Files"><U><B>comment</B></U></A></div> <bR> </td> <td valign="top" height=390 BGCOLOR="#FFFFFF" TEXT="#080000"> <div> Pin files define both top level and sub module IO. At the top level of a design the pin file is used to generate a pad ring. It also defines the pin locations, strength, type, speed, setup time, hold times, logic levels, and timing constraints. For the lower levels of a design the pin file is used to define the module's pin names. Pin file names must use a .pin extension, for example my_design.pin.</div> <bR> <div> <B> <A NAME="basic_pin_file_format"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>Basic Pin File Format</B></div> <div> The basic .pin file defines the IOs of a Verilog module or a VHDL entity. Pins may be either single wires or buses. Buses are defined as any signal name that ends in a number or a range of numbers, i.e both foo3 and foo[31:0] represent buses. In ordered to use numbered buses, i.e. foo2[31:0], you must set the HDLMAKER_TRAIL_NUM env variable to TRUE.</div> <bR> <div> For internal modules or entities only the signal names, bus ranges and pin types need be specified. The keyword #nopadring tells HDLmaker that no pad ring is required. The keywords #pins and #endpins delimit the start and end of the pin list.</div> <bR> <div> #nopadring</div> <div> #pins</div> <div> fb_data[32:0]           type = in;</div> <div> sysclk                  type = in;</div> <div> gblreset                type = in;</div> <div> tclk                    type = in;</div> <div> scan_enb                type = in;</div> <div> scan_in                 type = in;</div> <div> scan_out                type = out;</div> <div> mclock[15:5]            type = in;</div> <div> cmd_op[31:0]            type = in;</div> <div> chip[15:0]              type = in;</div> <div> done                    type = out;</div> <div> data[31:0]              type = out, comment = "Data outputs";</div> <div> enb_data_l[31:0]        type = out;</div> <div> enb_external_io_l[15:0] type = out;</div> <div> cntr[26:0]              type = out;</div> <div> enb_special_l[5:0]      type = out;</div> <div> special[5:0]            type = out;</div> <div> fb_special[5:0]         type = in;</div> <div> enb_special_l[5:0]      type = out;</div> <bR> <div> #endpins</div> <bR> <div> <B> <A NAME="top_level_pin_file_format"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>Top Level Pin File Format</B></div> <div> At the top level of a chip a pad ring is needed. The top level pin file defines not only the pin names but also the pin locations, drive strength, logic levels, tristate enables, IO flip flops and latches, clock enables, and setup and hold timing constraints. If the keyword #uselibrary is present, HDLmaker will directly instantiate the correct components, if #uselibrary is not present then HDLmaker will generate Verilog or VHDL code for the pad ring. For supported FPGAs the #uselibrary mechanism is preferred. For unsupported FPGAs and for ASICs the direct code mechanism works although it affords less control over the final output. Shown below is a typical Virtex pin files.</div> <bR> <div> #uselibrary</div> <div> #pins</div> <div> scan_tms                type = in,clk=tclk,pin = at10;</div> <div> scan_tdo                type = out,c2p=7,pin = at8;</div> <div> scan_tdi                type = in,p2s=7,pin = at7;</div> <div> tclkin                  type = clkp,pin = aw19;</div> <div> tclk                    type = internal;</div> <bR> <div> data[15:5]              type = inout, tristate=enb_l, clk=sysclk, pin =[v35, u35, ac35, ab35, ar23, ar22, ar18, ac5, ab5, u5, v5], comment = "Bidirectional data bus";</div> <div> enb_l                   type = internal;</div> <div> vclock                  type = clkp,pin = d21,comment = "100 Mhz Clock";</div> <div> clkreset                type = in,pin = [e22];</div> <div> reset                   type = in,pin=e23;</div> <bR> <div> sysclk                  type = internal;</div> <bR> <div> vclock                  type = clkp,pin = d21;</div> <bR> <bR> <div> #endpins</div> <bR> <div> <B> <A NAME="_uselibrary"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>#uselibrary</B></div> <bR> <div> #uselibrary is for padrings. It causes HDLmaker to directly instantiantiate IO buffers, flip flops and latches.</div> <bR> <div> <B> <A NAME="_nopadring"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>#nopadring</B></div> <bR> <div> #nopadring is for internal components that do not require pad rings.</div> <bR> <div> <B> <A NAME="_frczero"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>#frczero</B></div> <bR> <div> #frczero assigns a 0 to all of the outputs. This useful at the start of a project when most of the code hasn't been written. frzero elimates the Xs.</div> <bR> <div> <B>#tristate_prefix,#prefix,#postfix</B></div> <bR> <div> Unless #nopadring is specified, Hdlmaker generates module/entity pin names of the form</div> <bR> <div> 'prefix'_name_'postfix for inputs and outputs</div> <div> 'tristate_prefix'_name_'postfix for inouts</div> <bR> <div> The defaults are </div> <bR> <div> prefix ""</div> <div> postfix "pin"</div> <div> tristate_prefix "t_"</div> <bR> <div> Thus for the signall foo the external name would be</div> <bR> <div> foo_pin if foo is an input or output</div> <div> t_foo_pin if foo is an tristate output on inout.</div> <bR> <div> The tristate_prefix, prefix and postfix may be overridden with the #tristate_prefix, #prefix and #postfix statements.</div> <bR> <div> Example:</div> <div> #tristate_prefix "tri_";</div> <div> #prefix "pad_";</div> <div> #postfix "";</div> <bR> <div> would generate </div> <div> pad_foo if foo is an input or an output.</div> <div> tri_pad_foo if foo is a tristate output or inout.</div> <bR> <div> <B> <A NAME="signal_name_formats"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>Signal name formats</B></div> <bR> <div> The legal characters for signal names are letters, numbers and underscore. If the signal refers to a bus or bus fragment then the format is signal_name[#], signal_name[#:#] or signal_name[#,#,#:#] where : represents a range. Examples of legal names are</div> <bR> <div> foo</div> <div> foo_bar[3]</div> <div> myname[8:15]</div> <div> yourname[31:0]</div> <div> bar[0,1,3:5,15:12]</div> <bR> <div> Unlike VHDL and Verilog, HDLmaker supports sparse buses and arbitrary ordering. HDLmaker will straighten out the bus numbering and generate legal Verilog and VHDL code.</div> <bR> <div> <B> <A NAME="default_signal_names_"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>Default signal names.</B></div> <bR> <div> For bidirectional IOs hdlmaker has the following conventions</div> <bR> <div> name        Internal source name</div> <div> fb_name     Feedback signal from the IO pin</div> <div> name_pin    Name of pin.</div> <bR> <div> For all unidirectional pins</div> <bR> <div> name        Internal signal name</div> <div> name_pin    Pin name</div> <bR> <div> <B> <A NAME="type_field"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>Type field</B></div> <bR> <div> The type field specifies the function of the pin. The available types are</div> <div> in            input</div> <div> out           output</div> <div> regout        registered outputs, adds the Verilog reg declaration</div> <div> inout         bidirectional or tristate</div> <div> rsvd          reserved (used to preserve a pin number for future use)</div> <div> clks          Xilinx secondary clock buffer</div> <div> clkp          Xilinx primary clock buffer</div> <div> internal      Internal control signal (for example clock enables or tristate enables)</div> <div> vcc           Vcc pin</div> <div> vcc_io        IO VCC pin</div> <div> gnd           Ground pin</div> <div> vdd           Vdd pin</div> <div> ldc           Xilinx ldc pin</div> <div> cclk          Xilinx cclk</div> <div> prog          Xilinx prog pin</div> <div> din           Xilinx din pin</div> <div> dout          Xilinx dout pin</div> <div> init          Xilinx init pin</div> <div> gts           Xilinx CPLD gts pin</div> <div> gsr           Xilinx CPLD gsr pin</div> <div> mode          Xilinx mode pin</div> <div> tms           Xilinx JTAG tms pin</div> <div> tdi           Xilinx JTAG tdi pin</div> <div> tdo           Xilinx JTAG tdo pin</div> <div> done          Xilinx DONE pin</div> <div> vref          Virtex2 VREF pin</div> <div> vrp           Virtex2 VRP pin</div> <div> vrn           Virtex2 VNR pin</div> <div> powerdwn      Virtex2 power down pin</div> <div> vccaux        Virtex2 VCCAUX pin</div> <div> vccint        Virtex2 VCC internal pin</div> <div> dxn           Virtex2 DXN pin</div> <div> dxp           Virtex2 DXP pin</div> <div> vbatt         Virtex2 VBATT pin</div> <div> hswap         Virtex2 HSWAP pin</div> <div> iff_in         Virtex2, Spartan 3, Virtex2p, Virtex 4, Differential Input</div> <div> diff_out    Virtex2, Spartan 3, Virtex2p, Virtex 4, Differential Output</div> <div> diff_io        Virtex2, Spartan 3, Virtex2p, Virtex 4, Differential IO</div> <div> diff_clk    Virtex2, Spartan 3, Virtex2p, Virtex 4, Differential Clock Input</div> <div> direct_in    Virtex2, Spartan 3, Virtex2p, Virtex 4, Direct input (no buffer, use for RocketIO which includes the buffer)</div> <div> direct_out    Virtex2, Spartan 3, Virtex2p, Virtex 4, Direct output (no buffer, use for RocketIO which includes the buffer)</div> <div> ddr_in        Virtex2, Spartan 3, Virtex2p, Virtex 4, Double data rate input</div> <div> ddr_out        Virtex2, Spartan 3, Virtex2p, Virtex 4, Double data rate output</div> <div> ddr_io        Virtex2, Spartan 3, Virtex2p, Virtex 4, Double data rate I/O</div> <div> ddr_dqs        Stratix, Double data rate DQS pin (Altera only)</div> <div> ddr_i_oreg    Virtex2, Spartan 3, Virtex2p, Virtex 4, Double data rate output, combinatorial input (Xilinx DQS use)</div> <div> diff_ddr_in    Virtex2, Spartan 3, Virtex2p, Virtex 4, Differential double data rate in</div> <div> diff_ddr_out    Virtex2, Spartan 3, Virtex2p, Virtex 4, Differential double data rate out</div> <bR> <bR> <div> The special purpose pins are used for PC board netlist generation. Obviously vccs, gnds or the programming pins are not used for simulation or synthesis, however they are required for the board level design. HDLmaker maintains a library of package pinouts for most Xilinx parts which allows it to check for legal pin locations and allows it to automatically pin out a part.</div> <bR> <div> <B> <A NAME="clkinclkoutclklchtriclk"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>clk,inclk,outclk,lch,triclk</B></div> <bR> <div> The clk statements specfy the clocks or latch enables to the IO registers.</div> <bR> <div> clk=sysclk          positive edge triggered clock to input and output regs.</div> <div> clk=!sysclk         negative edge triggered clock to input and output regs.</div> <div> lch=sysclk          High true latch enable (inputs only)</div> <div> lch=!sysclk         Low true latch enable(inputs only)</div> <div> inclk=sysclk        positive edge triggered input clock</div> <div> inclk=!sysclk       negative edge triggered input clock</div> <div> outclk=sysclk       positive edge triggered output clock</div> <div> outclk=!sysclk      negative edge triggered output clock</div> <div> triclk=sysclk       positive edge triggered tristate enable reg </div> <div> triclk=!sysclk      negative edge triggered tristate enable reg</div> <bR> <div> If no clk statement is present then the IO pin is assumed to be combinatorial</div> <bR> <div> <B> <A NAME="inclkenboutclkenbioclkenbtriclkenb"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>inclkenb,outclkenb,ioclkenb,triclkenb</B></div> <bR> <div> Input and output clock enables are specified as follows:</div> <bR> <div> inclkenb=enb_name     Input flipflop enable</div> <div> outclkenb=enb_name    Output enable</div> <div> inoutenb=enb_name     Both</div> <bR> <div> Tristate enable register clock enable is specified as follows:</div> <bR> <div> triclkenb = enb_name</div> <bR> <div> <B> <A NAME="enable"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>enable</B></div> <bR> <div> The tristate buffer enable, high = enable, low = disable(tristate). The enable statement has the form:</div> <bR> <div> enable=!enb_l     Enable the output of enable is low</div> <div> enable=enb        Enable the output if enable_l is high</div> <bR> <div> <B> <A NAME="tristate"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>tristate</B></div> <bR> <div> The tristate buffer disable, high = disable, low = enable. The tristate statement has the form:</div> <bR> <div> tristate=!enb      Enable the output of enb is high</div> <div> tristate=enb_l     Enable the output if enb_l is low</div> <bR> <div> <B> <A NAME="triresetlevel"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>triresetlevel</B></div> <bR> <div> The default tristate enable register reset level is 1. If a clear is desired then use</div> <bR> <div> triresetlevel=0</div> <bR> <div> <B> <A NAME="resetlevel"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>resetlevel</B></div> <bR> <div> The default input and output register reset level is 0. If a preset is desired then use</div> <bR> <div> resetlevel=1</div> <bR> <div> <B> <A NAME="resistor"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>resistor</B></div> <bR> <div> Pullup and pulldown resistors may be specified as follows:</div> <bR> <div> resistor=pullup</div> <div> resistor=pulldown</div> <bR> <div> <B> <A NAME="speedsetup"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>speed,setup</B></div> <bR> <div> The speed of the outputs and hold time characteristics of the inputs may be controled as follows:</div> <bR> <div> speed=slow            Use the slew limited output buffers, default is the fast buffers</div> <div> speed=fast            Use the fast output buffers, default is the fast buffers</div> <div> setup=nodelay         Use the fast input buffers, some hold time will be required (XC4000 families only).</div> <div> setup=nohold          Use the slow input buffers, hold time is 0, setup time is longer, XC4000 families only.</div> <bR> <div> <B> <A NAME="p2sc2p"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>p2s,c2p</B></div> <bR> <div> Xilinx timing constraints.  P2S specifies setup time in nanoseconds, C2P specifies clock to output in nanoseconds.</div> <bR> <div> p2s=16                The pin to setup time of this pin is 16 ns.</div> <div> c2p=20                The clock to pin time of this pin is 20 ns.</div> <bR> <div> <B> <A NAME="alias"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>alias</B></div> <bR> <div> The alias statement is used to provide an additional connection to a pin. Xilinx inputs can </div> <div> be both registered and combinatorial at the same time. An example is shown below:</div> <bR> <div> txbusy             type = in,clk = sysclk,pin=128,resetlevel=1;</div> <div> nxttxbusy          type = in,alias = txbusy,p2s=16 ;</div> <bR> <div> txbusy is registered,nxttxbusy is combinatorial.</div> <bR> <div> <B> <A NAME="pin"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>pin</B></div> <bR> <div> The pin statement specifies the pin numbers. The pin list is an arbitrary list of numbers. For packages that uses strictly numeric pin numbers, such as QFPs,  ranges are supported. For packages that use alpha numeric numbering, such as BGAs, ranges should be avoided.</div> <bR> <div> Examples:</div> <bR> <div> pin=12</div> <div> pin=[0:3,8,31:20,7]</div> <bR> <div> pin = [v35, u35, ac35, ab35, ar23, ar22, ar18, ac5, ab5, u5,v5,e18,e17]</div> <bR> <div> <B> <A NAME="strength"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>strength</B></div> <bR> <div> The strength statement spcifies the drive strength of the output buffer. For Virtex the valid values are 2,4,6,8,12,16 & 24. </div> <bR> <div> strength=24</div> <bR> <div> <B> <A NAME="logic"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>logic</B></div> <bR> <div> The logic statement specifies the logic levels. The default is logic family is LVTTL. The strength, fast and slow statements should only be used in conjunction with the default LVTTL levels. </div> <bR> <div> The valid exotic logic levels for Virtex are:</div> <bR> <div> logic=GTL</div> <div> logic=GTLP</div> <div> logic=HSTL_I</div> <div> logic=HSTL_III</div> <div> logic=HSTL_IV</div> <div> logic=LVCMOS2</div> <div> logic=PCI33_3</div> <div> logic=PCI33_5</div> <div> logic=PCI66_3</div> <div> logic=SSTL2_I</div> <div> logic=SSTL2_II</div> <div> logic=SSTL3_I</div> <div> logic=SSTL3_II</div> <div> <B> <A NAME="comment"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>comment</B></div> <div> Add a comment to an IO declaration </div> <bR> <div> comment= "125Mhz Clock"</div> <bR> <div> Comments are in quoted strings, they may be multiple lines long and the printf characters \n, \r and \t may be used.</div> <bR> </td> </tr></table></body>