Pin files define both top level and sub module IO. At the top level of a design the pin file is used to generate a pad ring. It also defines the pin locations, strength, type, speed, setup time, hold times, logic levels, and timing constraints. For the lower levels of a design the pin file is used to define the module's pin names. Pin file names must use a .pin extension, for example my_design.pin.
Basic Pin File Format
The basic .pin file defines the IOs of a Verilog module or a VHDL entity. Pins may be either single wires or buses. Buses are defined as any signal name that ends in a number or a range of numbers, i.e both foo3 and foo[31:0] represent buses. In ordered to use numbered buses, i.e. foo2[31:0], you must set the HDLMAKER_TRAIL_NUM env variable to TRUE.
For internal modules or entities only the signal names, bus ranges and pin types need be specified. The keyword #nopadring tells HDLmaker that no pad ring is required. The keywords #pins and #endpins delimit the start and end of the pin list.
#nopadring
#pins
fb_data[32:0] type = in;
sysclk type = in;
gblreset type = in;
tclk type = in;
scan_enb type = in;
scan_in type = in;
scan_out type = out;
mclock[15:5] type = in;
cmd_op[31:0] type = in;
chip[15:0] type = in;
done type = out;
data[31:0] type = out, comment = "Data outputs";
enb_data_l[31:0] type = out;
enb_external_io_l[15:0] type = out;
cntr[26:0] type = out;
enb_special_l[5:0] type = out;
special[5:0] type = out;
fb_special[5:0] type = in;
enb_special_l[5:0] type = out;
#endpins
Top Level Pin File Format
At the top level of a chip a pad ring is needed. The top level pin file defines not only the pin names but also the pin locations, drive strength, logic levels, tristate enables, IO flip flops and latches, clock enables, and setup and hold timing constraints. If the keyword #uselibrary is present, HDLmaker will directly instantiate the correct components, if #uselibrary is not present then HDLmaker will generate Verilog or VHDL code for the pad ring. For supported FPGAs the #uselibrary mechanism is preferred. For unsupported FPGAs and for ASICs the direct code mechanism works although it affords less control over the final output. Shown below is a typical Virtex pin files.
#uselibrary
#pins
scan_tms type = in,clk=tclk,pin = at10;
scan_tdo type = out,c2p=7,pin = at8;
scan_tdi type = in,p2s=7,pin = at7;
tclkin type = clkp,pin = aw19;
tclk type = internal;
data[15:5] type = inout, tristate=enb_l, clk=sysclk, pin =[v35, u35, ac35, ab35, ar23, ar22, ar18, ac5, ab5, u5, v5], comment = "Bidirectional data bus";
enb_l type = internal;
vclock type = clkp,pin = d21,comment = "100 Mhz Clock";
clkreset type = in,pin = [e22];
reset type = in,pin=e23;
sysclk type = internal;
vclock type = clkp,pin = d21;
#endpins
#uselibrary
#uselibrary is for padrings. It causes HDLmaker to directly instantiantiate IO buffers, flip flops and latches.
#nopadring
#nopadring is for internal components that do not require pad rings.
#frczero
#frczero assigns a 0 to all of the outputs. This useful at the start of a project when most of the code hasn't been written. frzero elimates the Xs.
#tristate_prefix,#prefix,#postfix
Unless #nopadring is specified, Hdlmaker generates module/entity pin names of the form
'prefix'_name_'postfix for inputs and outputs
'tristate_prefix'_name_'postfix for inouts
The defaults are
prefix ""
postfix "pin"
tristate_prefix "t_"
Thus for the signall foo the external name would be
foo_pin if foo is an input or output
t_foo_pin if foo is an tristate output on inout.
The tristate_prefix, prefix and postfix may be overridden with the #tristate_prefix, #prefix and #postfix statements.
Example:
#tristate_prefix "tri_";
#prefix "pad_";
#postfix "";
would generate
pad_foo if foo is an input or an output.
tri_pad_foo if foo is a tristate output or inout.
Signal name formats
The legal characters for signal names are letters, numbers and underscore. If the signal refers to a bus or bus fragment then the format is signal_name[#], signal_name[#:#] or signal_name[#,#,#:#] where : represents a range. Examples of legal names are
foo
foo_bar[3]
myname[8:15]
yourname[31:0]
bar[0,1,3:5,15:12]
Unlike VHDL and Verilog, HDLmaker supports sparse buses and arbitrary ordering. HDLmaker will straighten out the bus numbering and generate legal Verilog and VHDL code.
Default signal names.
For bidirectional IOs hdlmaker has the following conventions
name Internal source name
fb_name Feedback signal from the IO pin
name_pin Name of pin.
For all unidirectional pins
name Internal signal name
name_pin Pin name
Type field
The type field specifies the function of the pin. The available types are
in input
out output
regout registered outputs, adds the Verilog reg declaration
inout bidirectional or tristate
rsvd reserved (used to preserve a pin number for future use)
clks Xilinx secondary clock buffer
clkp Xilinx primary clock buffer
internal Internal control signal (for example clock enables or tristate enables)
vcc Vcc pin
vcc_io IO VCC pin
gnd Ground pin
vdd Vdd pin
ldc Xilinx ldc pin
cclk Xilinx cclk
prog Xilinx prog pin
din Xilinx din pin
dout Xilinx dout pin
init Xilinx init pin
gts Xilinx CPLD gts pin
gsr Xilinx CPLD gsr pin
mode Xilinx mode pin
tms Xilinx JTAG tms pin
tdi Xilinx JTAG tdi pin
tdo Xilinx JTAG tdo pin
done Xilinx DONE pin
vref Virtex2 VREF pin
vrp Virtex2 VRP pin
vrn Virtex2 VNR pin
powerdwn Virtex2 power down pin
vccaux Virtex2 VCCAUX pin
vccint Virtex2 VCC internal pin
dxn Virtex2 DXN pin
dxp Virtex2 DXP pin
vbatt Virtex2 VBATT pin
hswap Virtex2 HSWAP pin
iff_in Virtex2, Spartan 3, Virtex2p, Virtex 4, Differential Input
diff_out Virtex2, Spartan 3, Virtex2p, Virtex 4, Differential Output
diff_io Virtex2, Spartan 3, Virtex2p, Virtex 4, Differential IO
diff_clk Virtex2, Spartan 3, Virtex2p, Virtex 4, Differential Clock Input
direct_in Virtex2, Spartan 3, Virtex2p, Virtex 4, Direct input (no buffer, use for RocketIO which includes the buffer)
direct_out Virtex2, Spartan 3, Virtex2p, Virtex 4, Direct output (no buffer, use for RocketIO which includes the buffer)
ddr_in Virtex2, Spartan 3, Virtex2p, Virtex 4, Double data rate input
ddr_out Virtex2, Spartan 3, Virtex2p, Virtex 4, Double data rate output
ddr_io Virtex2, Spartan 3, Virtex2p, Virtex 4, Double data rate I/O
ddr_dqs Stratix, Double data rate DQS pin (Altera only)
ddr_i_oreg Virtex2, Spartan 3, Virtex2p, Virtex 4, Double data rate output, combinatorial input (Xilinx DQS use)
diff_ddr_in Virtex2, Spartan 3, Virtex2p, Virtex 4, Differential double data rate in
diff_ddr_out Virtex2, Spartan 3, Virtex2p, Virtex 4, Differential double data rate out
The special purpose pins are used for PC board netlist generation. Obviously vccs, gnds or the programming pins are not used for simulation or synthesis, however they are required for the board level design. HDLmaker maintains a library of package pinouts for most Xilinx parts which allows it to check for legal pin locations and allows it to automatically pin out a part.
clk,inclk,outclk,lch,triclk
The clk statements specfy the clocks or latch enables to the IO registers.
clk=sysclk positive edge triggered clock to input and output regs.
clk=!sysclk negative edge triggered clock to input and output regs.
lch=sysclk High true latch enable (inputs only)
lch=!sysclk Low true latch enable(inputs only)
inclk=sysclk positive edge triggered input clock
inclk=!sysclk negative edge triggered input clock
outclk=sysclk positive edge triggered output clock
outclk=!sysclk negative edge triggered output clock
triclk=sysclk positive edge triggered tristate enable reg
triclk=!sysclk negative edge triggered tristate enable reg
If no clk statement is present then the IO pin is assumed to be combinatorial
inclkenb,outclkenb,ioclkenb,triclkenb
Input and output clock enables are specified as follows:
inclkenb=enb_name Input flipflop enable
outclkenb=enb_name Output enable
inoutenb=enb_name Both
Tristate enable register clock enable is specified as follows:
triclkenb = enb_name
enable
The tristate buffer enable, high = enable, low = disable(tristate). The enable statement has the form:
enable=!enb_l Enable the output of enable is low
enable=enb Enable the output if enable_l is high
tristate
The tristate buffer disable, high = disable, low = enable. The tristate statement has the form:
tristate=!enb Enable the output of enb is high
tristate=enb_l Enable the output if enb_l is low
triresetlevel
The default tristate enable register reset level is 1. If a clear is desired then use
triresetlevel=0
resetlevel
The default input and output register reset level is 0. If a preset is desired then use
resetlevel=1
resistor
Pullup and pulldown resistors may be specified as follows:
resistor=pullup
resistor=pulldown
speed,setup
The speed of the outputs and hold time characteristics of the inputs may be controled as follows:
speed=slow Use the slew limited output buffers, default is the fast buffers
speed=fast Use the fast output buffers, default is the fast buffers
setup=nodelay Use the fast input buffers, some hold time will be required (XC4000 families only).
setup=nohold Use the slow input buffers, hold time is 0, setup time is longer, XC4000 families only.
p2s,c2p
Xilinx timing constraints. P2S specifies setup time in nanoseconds, C2P specifies clock to output in nanoseconds.
p2s=16 The pin to setup time of this pin is 16 ns.
c2p=20 The clock to pin time of this pin is 20 ns.
alias
The alias statement is used to provide an additional connection to a pin. Xilinx inputs can
be both registered and combinatorial at the same time. An example is shown below:
txbusy type = in,clk = sysclk,pin=128,resetlevel=1;
nxttxbusy type = in,alias = txbusy,p2s=16 ;
txbusy is registered,nxttxbusy is combinatorial.
pin
The pin statement specifies the pin numbers. The pin list is an arbitrary list of numbers. For packages that uses strictly numeric pin numbers, such as QFPs, ranges are supported. For packages that use alpha numeric numbering, such as BGAs, ranges should be avoided.
Examples:
pin=12
pin=[0:3,8,31:20,7]
pin = [v35, u35, ac35, ab35, ar23, ar22, ar18, ac5, ab5, u5,v5,e18,e17]
strength
The strength statement spcifies the drive strength of the output buffer. For Virtex the valid values are 2,4,6,8,12,16 & 24.
strength=24
logic
The logic statement specifies the logic levels. The default is logic family is LVTTL. The strength, fast and slow statements should only be used in conjunction with the default LVTTL levels.
The valid exotic logic levels for Virtex are:
logic=GTL
logic=GTLP
logic=HSTL_I
logic=HSTL_III
logic=HSTL_IV
logic=LVCMOS2
logic=PCI33_3
logic=PCI33_5
logic=PCI66_3
logic=SSTL2_I
logic=SSTL2_II
logic=SSTL3_I
logic=SSTL3_II
comment
Add a comment to an IO declaration
comment= "125Mhz Clock"
Comments are in quoted strings, they may be multiple lines long and the printf characters \n, \r and \t may be used.