Language

<body topmargin=0 leftmargin=0 marginheight=0 marginwidth=0> <table cellpadding=0 cellspacing=0 border=0><tr> <td valign="top" colspan=2 height=90 BGCOLOR="#CC9900" TEXT="#080000" bgproperties="fixed" background="045005a0dwnjzk.gif"> <div> <A HREF="index.htm" TARGET="_top" TITLE="HDLmaker"><U><B>home</B></U></A><B>     | </B><B> </B><B> </B><B>  </B><FONT SIZE="5" COLOR="#FFCC66" FACE="Arial" ><B>HDLmaker</B></FONT></div> <div> <A HREF="id22.htm" TARGET="_top" TITLE="Top Files"><U><B>Top Files</B></U></A><B>   |   </B><A HREF="id23.htm" TARGET="_top" TITLE="Pin Files"><U><B>Pin Files</B></U></A><B>   |   </B><B>Language</B><B>   |   </B><A HREF="id28.htm" TARGET="_top" TITLE="Directory Organization"><U><B>Directory Organization</B></U></A><B>   |   </B><A HREF="id29.htm" TARGET="_top" TITLE="Simulation"><U><B>Simulation</B></U></A><B>   |   </B><A HREF="id30.htm" TARGET="_top" TITLE="Synthesis"><U><B>Synthesis</B></U></A><B>   |   </B><A HREF="id33.htm" TARGET="_top" TITLE="Xilinx Tools"><U><B>Xilinx Tools</B></U></A><B>   |   </B><A HREF="id25.htm" TARGET="_top" TITLE="Examples"><U><B>Examples</B></U></A></div> <div> </div> </td> </tr><tr> <td valign="top" width=210 BGCOLOR="#FFFFFF" TEXT="#080000"> <div> Language</div> <div> <B><IMG SRC="06169830.gif" border=0 width="105" height="131" ALIGN="BOTTOM" HSPACE="0" VSPACE="0"></B><A HREF="http://www.polybus.com" TARGET="_top" TITLE="http://www.polybus.com"><U><B>Polybus</B></U></A></div> <bR> <div> <A HREF="id24_m.htm#variables" TARGET="TRLX_Middle" TITLE="Language"><U><B>Variables</B></U></A></div> <div> <A HREF="id24_m.htm#int" TARGET="TRLX_Middle" TITLE="Language"><U><B>Int</B></U></A></div> <div> <A HREF="id24_m.htm#strings" TARGET="TRLX_Middle" TITLE="Language"><U><B>Strings</B></U></A></div> <div> <A HREF="id24_m.htm#builtin_variables" TARGET="TRLX_Middle" TITLE="Language"><U><B>Builtin Variables</B></U></A></div> <div> <A HREF="id24_m.htm#lexical_scope" TARGET="TRLX_Middle" TITLE="Language"><U><B>Lexical Scope</B></U></A></div> <bR> <div> <A HREF="id24_m.htm#_assign" TARGET="TRLX_Middle" TITLE="Language"><U><B>#assign</B></U></A></div> <div> <A HREF="id24_m.htm#_if_else" TARGET="TRLX_Middle" TITLE="Language"><U><B>#if,else</B></U></A></div> <div> <A HREF="id24_m.htm#_for" TARGET="TRLX_Middle" TITLE="Language"><U><B>#for</B></U></A></div> <div> <A HREF="id24_m.htm#_while" TARGET="TRLX_Middle" TITLE="Language"><U><B>#while</B></U></A></div> <bR> <div> <A HREF="id24_m.htm#code_generation_example" TARGET="TRLX_Middle" TITLE="Language"><U><B>Code Generation Example</B></U></A></div> <div> <A HREF="id24_m.htm#loop_top" TARGET="TRLX_Middle" TITLE="Language"><U><B>loop.top</B></U></A></div> <div> <A HREF="id24_m.htm#loop_v" TARGET="TRLX_Middle" TITLE="Language"><U><B>loop.v</B></U></A></div> <div> <A HREF="id24_m.htm#loop_vhd" TARGET="TRLX_Middle" TITLE="Language"><U><B>loop.vhd</B></U></A></div> <bR> <bR> </td> <td valign="top" height=390 BGCOLOR="#FFFFFF" TEXT="#080000"> <div> HDLmaker supports a C like language that is used to generate complex design. The language supports integer and string arithmetic, conditional branching, and loops.</div> <bR> <div> <B> <A NAME="variables"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>Variables</B></div> <div> HDLmaker has two data types, integers and strings. Ints are 32 bit signed integers, strings are radix 36 numbers which are described below. Variables are declared with the #int and the #string statements.</div> <bR> <div> #int i,j,k,index;</div> <div> #string a_bus,b_bus;</div> <bR> <div> The initial value of a variable is inherited from the caller, i.e. if a top file declares a variable foo and assigns a value to it and then calls bar.top the initial value that the module bar.top sees is the value assigned in the calling module. Initial values may be assigned from the command line with the switches -int,-string and -variables. -int and -string are used for individula variables, -variables calls a file which assigns initial values to multiple variables.</div> <bR> <div> hdlmaker -int foo 12 -string my_str THIS_IS_MY_String -variables var.txt bar.top</div> <bR> <div> The format for a variables file is,</div> <div> #int var_a 10;</div> <div> #int var_b 15;</div> <div> #string str_var_a hello_world;</div> <div> #string str_var_b glad_to_see_you;</div> <bR> <div> <B> <A NAME="int"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>Int</B></div> <div> Ints are signed longs. HDLmaker supports the full set of C integer and logical operations.</div> <div> +</div> <div> -</div> <div> *</div> <div> /</div> <div> &</div> <div> |</div> <div> ^</div> <div> !</div> <div> ~</div> <div> ++</div> <div> --</div> <div> +=</div> <div> -=</div> <div> *=</div> <div> /=</div> <div> &=</div> <div> |=</div> <div> ^=</div> <div> >></div> <div> <<</div> <div> <> (Rotate)</div> <bR> <div> Conditionals</div> <div> ></div> <div> <</div> <div> >=</div> <div> <=</div> <div> ==</div> <bR> <div> <B> <A NAME="strings"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>Strings</B></div> <div> Strings are limited the characters a-z 0-9 and _. The radix26 variable determines if radix 26 or radix 36 arithmetic is used. For arithmetic operations strings are treated as either radix 36 numbers where the characters have the decimal value:</div> <div> 0-9       0-9</div> <div> a-z       10-25</div> <div> or as radix 26 numbers where the characters have the decimal values,</div> <div> a-z       0-25</div> <bR> <div> The underscore is used as a field delimiter. To illustrate how string arithmetic works consider the following two radix 36 examples.</div> <bR> <div> az + 1 </div> <div> --------</div> <div> b0</div> <bR> <div> a_z +1</div> <div> --------</div> <div> a_10</div> <bR> <div> In the first example az is treated as a single number and the carry out of z +1 is added to the next character. In the second example the field delimiter separates the first field, a, from the second, z. In this case z + 1 is 10.</div> <bR> <div> To understand the difference between radix 26 and radix 36 arithmetic consider the following examples</div> <div> radix 26</div> <div> z + 1</div> <div> -----</div> <div> ba</div> <bR> <div> radix 36</div> <div> z + 1</div> <div> -----</div> <div> 10</div> <bR> <div> The following operations are supported on strings,</div> <div> +</div> <div> -</div> <div> *</div> <div> /</div> <div> ~</div> <div> &</div> <div> |</div> <div> ^</div> <div> $ (concatenate)</div> <div> ++</div> <div> --</div> <div> +=</div> <div> -=</div> <div> *=</div> <div> /=</div> <bR> <div> Conditionals</div> <div> ==</div> <div> >=</div> <div> <=</div> <div> <</div> <div> ></div> <div> <B> <A NAME="builtin_variables"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>Builtin Variables</B></div> <div> HDLmaker parameters/switche values are available as builtin variables. The Built in variables are,</div> <div> <TABLE BORDER="2" CELLPADDING="2" CELLSPACING="1" WIDTH="506" BORDERCOLORLIGHT="#C0C0C0" BORDERCOLORDARK="#808080" FRAME="BOX" RULES="ALL" ALIGN="BOTTOM" HSPACE="0" VSPACE="0" > <tR> <tD VALIGN=TOP HEIGHT= 20 WIDTH="147"><div> <B>Variable</B></div> </tD> <tD VALIGN=TOP WIDTH="72"><div> <B>Type</B></div> </tD> <tD VALIGN=TOP WIDTH="144"><div> <B>Description</B></div> </tD> <tD VALIGN=TOP WIDTH="110"><div> <B>Values</B></div> </tD> </tR> <tR> <tD VALIGN=TOP HEIGHT= 38 ><NOBR><div> hdl_simulate_mode</div> </NOBR></tD> <tD VALIGN=TOP WIDTH="72"><div> int</div> </tD> <tD VALIGN=TOP WIDTH="144"><div> Simulate or Synthesis mode</div> </tD> <tD VALIGN=TOP WIDTH="110"><div> 0 Synthesis</div> <div> 1 Simulate</div> </tD> </tR> <tR> <tD VALIGN=TOP HEIGHT= 150 WIDTH="147"><div> hdl_simulator</div> </tD> <tD VALIGN=TOP WIDTH="72"><div> string</div> </tD> <tD VALIGN=TOP WIDTH="144"><div> Simulator</div> </tD> <tD VALIGN=TOP><NOBR><div> "leapfrog",</div> <div> "verilogxl",</div> <div> "modeltech",</div> <div> "vcs",</div> <div> "finsim",</div> <div> "ncverilog",</div> <div> "synopsysvss",</div> <div> "ncsim"</div> </NOBR></tD> </tR> <tR> <tD VALIGN=TOP HEIGHT= 168 WIDTH="147"><div> hdl_synthesys</div> </tD> <tD VALIGN=TOP WIDTH="72"><div> string</div> </tD> <tD VALIGN=TOP WIDTH="144"><div> Synthesis tool</div> </tD> <tD VALIGN=TOP><NOBR><div> "synopsys",</div> <div> "synplicity",</div> <div> "fpgaexpress",</div> <div> "exemplar",</div> <div> "leonardo",</div> <div> "rtlc",</div> <div> "xst",</div> <div> "quartus",</div> <div> "precision"</div> </NOBR></tD> </tR> <tR> <tD VALIGN=TOP HEIGHT= 19 WIDTH="147"><div> hdl_family</div> </tD> <tD VALIGN=TOP WIDTH="72"><div> string</div> </tD> <tD VALIGN=TOP WIDTH="144"><div> FPGA family</div> </tD> <tD VALIGN=TOP><NOBR><div> virtex,virtex2...</div> </NOBR></tD> </tR> <tR> <tD VALIGN=TOP HEIGHT= 19 WIDTH="147"><div> hdl_package</div> </tD> <tD VALIGN=TOP WIDTH="72"><div> string</div> </tD> <tD VALIGN=TOP><NOBR><div> FPGA package</div> </NOBR></tD> <tD VALIGN=TOP WIDTH="110"><div> ff1152...</div> </tD> </tR> <tR> <tD VALIGN=TOP HEIGHT= 19 WIDTH="147"><div> hdl_speed</div> </tD> <tD VALIGN=TOP WIDTH="72"><div> string</div> </tD> <tD VALIGN=TOP WIDTH="144"><div> FPGA speed</div> </tD> <tD VALIGN=TOP WIDTH="110"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="19" ALIGN="bottom" WIDTH="110" HSPACE="0" VSPACE="0"></tD> </tR> <tR> <tD VALIGN=TOP HEIGHT= 19 WIDTH="147"><div> hdl_company</div> </tD> <tD VALIGN=TOP WIDTH="72"><div> string</div> </tD> <tD VALIGN=TOP><NOBR><div> Company name</div> </NOBR></tD> <tD VALIGN=TOP WIDTH="110"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="19" ALIGN="bottom" WIDTH="110" HSPACE="0" VSPACE="0"></tD> </tR> <tR> <tD VALIGN=TOP HEIGHT= 19 WIDTH="147"><div> hdl_engineer</div> </tD> <tD VALIGN=TOP WIDTH="72"><div> string</div> </tD> <tD VALIGN=TOP><NOBR><div> Engineers name</div> </NOBR></tD> <tD VALIGN=TOP WIDTH="110"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="19" ALIGN="bottom" WIDTH="110" HSPACE="0" VSPACE="0"></tD> </tR> <tR> <tD VALIGN=TOP HEIGHT= 19 WIDTH="147"><div> hdl_language</div> </tD> <tD VALIGN=TOP WIDTH="72"><div> string</div> </tD> <tD VALIGN=TOP WIDTH="144"><div> HDL language</div> </tD> <tD VALIGN=TOP><NOBR><div> verilog,vhdl</div> </NOBR></tD> </tR> </TABLE></div> <div> <B> <A NAME="lexical_scope"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>Lexical Scope</B></div> <div> Variable values and names are copied down to lower levels of the hierarchy, no values are returned. Passing a parameter from one level to the next is done by name. To make this clear consider the following example:</div> <bR> <div> #int num_rows, num_cols;</div> <bR> <div> #assign num_rows = 12;</div> <div> #assign num_cols = 16;</div> <bR> <div> #insert "sub_level.top";</div> <bR> <div> Inside sub_level.top we may use the values as follows:</div> <bR> <div> #int i,j;</div> <div> #for(i=0;i<num_rows;i++)</div> <div> {</div> <div>   #for(j=0;j<num_cols;j++)</div> <div>   {</div> <div>     ....</div> <div>   }</div> <div> }</div> <bR> <div> <B> <A NAME="_assign"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>#assign</B></div> <div> Assignment statements begin with the keyword #assign.</div> <bR> <div> #assign x = y + z;</div> <div> #assign myname = first_name $ last_name;</div> <bR> <div> <B> <A NAME="_if_else"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>#if, else</B></div> <div> #if is identical to the C if statement.</div> <bR> <div> #if(i == j)</div> <div> {</div> <div> }</div> <div> else</div> <div> {</div> <div> }</div> <bR> <div> <B> <A NAME="_for"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>#for</B></div> <div> #for(i=0;i<num_rows;i++)</div> <div> {</div> <div> }</div> <div> <B> <A NAME="_while"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>#while</B></div> <div> #while(i < 100)</div> <div> {</div> <div>  #assign i++;</div> <div> }</div> <div> <B> <A NAME="code_generation_example"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>Code generation example</B></div> <div> Below is an example of code generation using HDLmaker's macro language. In connection statements HDLmaker takes names literally unless the expression starts with either a quoted string or with a #, in which case it evaulates the expression.</div> <bR> <div> <B> <A NAME="loop_top"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>loop.top</B></div> <bR> <div> #module "loop";</div> <bR> <div> #include "loop.pin";</div> <bR> <div> #int i;</div> <div> #string reg;</div> <bR> <bR> <div> #insert "dregce32.v",</div> <div>       connect ce                    = ce[0],</div> <div>       connect q[31:0]               = reg_a[31:0];</div> <bR> <div> #assign reg = "reg_a";</div> <bR> <div> #for(i=0;i<2;i++)</div> <div> {</div> <div>       #insert "dregce32.v",</div> <div>             connect ce                      = ce[#i+1],</div> <div>             connect d[31:0]                 = "reg_a" + i[31:0],</div> <div>             connect q[31:0]                 = "reg_b" + i[31:0];</div> <div>       #assign reg++;</div> <div> }</div> <bR> <div> #insert "dregce32.v",</div> <div>       connect ce                              = ce[#i+1],</div> <div>       connect d[31:0]                         = #reg[31:0];</div> <bR> <div> <B> <A NAME="loop_v"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>loop.v</B></div> <bR> <div> module loop(</div> <div>             ce,</div> <div>             d,</div> <div>             gblreset,</div> <div>             q,</div> <div>             sysclk</div> <div>             );</div> <div>    //-- IO Declarations</div> <div>    input  [3:0] ce;</div> <div>    input  [31:0] d;</div> <div>    input       gblreset;</div> <div>    output [31:0] q;</div> <div>    input       sysclk;</div> <bR> <div>    //-- Signal Declarations</div> <bR> <div>    wire [31:0]    reg_a;</div> <div>    wire [31:0]    reg_b;</div> <div>    wire [31:0]    reg_c;</div> <bR> <bR> <bR> <bR> <bR> <div>    //-- Component Instance dregce32_1</div> <div>    dregce32 dregce32_1</div> <div>       (</div> <bR> <div>          .ce                              (ce[0]),</div> <div>          .d                               ({d[31:0]}),</div> <div>          .gblreset                        (gblreset),</div> <div>          .sysclk                          (sysclk),</div> <div>          .q                               ({reg_a[31:0]})</div> <div>       );</div> <bR> <div>    //-- Component Instance dregce32_2</div> <div>    dregce32 dregce32_2</div> <div>       (</div> <bR> <div>          .ce                              (ce[1]),</div> <div>          .d                               ({reg_a[31:0]}),</div> <div>          .gblreset                        (gblreset),</div> <div>          .sysclk                          (sysclk),</div> <div>          .q                               ({reg_b[31:0]})</div> <div>       );</div> <bR> <div>    //-- Component Instance dregce32_3</div> <div>    dregce32 dregce32_3</div> <div>       (</div> <bR> <div>          .ce                              (ce[2]),</div> <div>          .d                               ({reg_b[31:0]}),</div> <div>          .gblreset                        (gblreset),</div> <div>          .sysclk                          (sysclk),</div> <div>          .q                               ({reg_c[31:0]})</div> <div>       );</div> <bR> <div>    //-- Component Instance dregce32_4</div> <div>    dregce32 dregce32_4</div> <div>       (</div> <bR> <div>          .ce                              (ce[3]),</div> <div>          .d                               ({reg_c[31:0]}),</div> <div>          .gblreset                        (gblreset),</div> <div>          .sysclk                          (sysclk),</div> <div>          .q                               ({q[31:0]})</div> <div>       );</div> <div> endmodule</div> <bR> <div> <B> <A NAME="loop_vhd"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>loop.vhd</B></div> <div> library IEEE;</div> <div>       use IEEE.std_logic_1164.all;</div> <div>       use IEEE.std_logic_arith.all;</div> <div>       use IEEE.std_logic_unsigned.all;</div> <bR> <div> entity loop is</div> <div>       port (</div> <div>             ce_pin :in std_logic_vector (3 downto 0);</div> <div>             d_pin :in std_logic_vector (31 downto 0);</div> <div>             gblreset_pin :in std_logic;</div> <div>             q_pin :buffer std_logic_vector (31 downto 0);</div> <div>             sysclk_pin :in std_logic</div> <div>       );</div> <div>       end loop;</div> <bR> <div> architecture BEHAVIOR of loop is</div> <bR> <div> component dregce32</div> <div>       port (</div> <bR> <div>       sysclk,ce,gblreset      : in std_logic ;</div> <div>       d                 : in std_logic_vector (31 downto 0);</div> <div>       q                 : buffer std_logic_vector (31 downto 0)</div> <div>             );</div> <div> end component;</div> <bR> <bR> <div> --// signals begin here</div> <bR> <div> signal      ce    : std_logic_vector (3 downto 0);</div> <div> signal      d     : std_logic_vector (31 downto 0);</div> <div> signal      gblreset    : std_logic;</div> <div> signal      q     : std_logic_vector (31 downto 0);</div> <div> signal      reg_a : std_logic_vector (31 downto 0);</div> <div> signal      reg_b : std_logic_vector (31 downto 0);</div> <div> signal      reg_c : std_logic_vector (31 downto 0);</div> <div> signal      sysclk      : std_logic;</div> <bR> <bR> <bR> <bR> <div> begin</div> <bR> <bR> <bR> <div> dregce32_1: dregce32</div> <div>       port map (</div> <bR> <div>             sysclk => sysclk,</div> <div>             ce => ce (0),</div> <div>             gblreset => gblreset,</div> <div>             d (31 downto 0) => d (31 downto 0),</div> <div>             q (31 downto 0) => reg_a (31 downto 0)</div> <div>       );</div> <bR> <div> dregce32_2: dregce32</div> <div>       port map (</div> <bR> <div>             sysclk => sysclk,</div> <div>             ce => ce (1),</div> <div>             gblreset => gblreset,</div> <div>             d (31 downto 0) => reg_a (31 downto 0),</div> <div>             q (31 downto 0) => reg_b (31 downto 0)</div> <div>       );</div> <bR> <div> dregce32_3: dregce32</div> <div>       port map (</div> <bR> <div>             sysclk => sysclk,</div> <div>             ce => ce (2),</div> <div>             gblreset => gblreset,</div> <div>             d (31 downto 0) => reg_b (31 downto 0),</div> <div>             q (31 downto 0) => reg_c (31 downto 0)</div> <div>       );</div> <bR> <div> dregce32_4: dregce32</div> <div>       port map (</div> <bR> <div>             sysclk => sysclk,</div> <div>             ce => ce (3),</div> <div>             gblreset => gblreset,</div> <div>             d (31 downto 0) => reg_c (31 downto 0),</div> <div>             q (31 downto 0) => q (31 downto 0)</div> <div>       );</div> <div> end;</div> <bR> </td> </tr></table></body>