Examples

<body topmargin=0 leftmargin=0 marginheight=0 marginwidth=0> <table cellpadding=0 cellspacing=0 border=0><tr> <td valign="top" colspan=2 height=90 BGCOLOR="#CC9900" TEXT="#080000" bgproperties="fixed" background="045005a0dwnjzk.gif"> <div> <A HREF="index.htm" TARGET="_top" TITLE="HDLmaker"><U><B>home</B></U></A><B>     | </B><B> </B><B> </B><B>  </B><FONT SIZE="5" COLOR="#FFCC66" FACE="Arial" ><B>HDLmaker</B></FONT></div> <div> <A HREF="id22.htm" TARGET="_top" TITLE="Top Files"><U><B>Top Files</B></U></A><B>   |   </B><A HREF="id23.htm" TARGET="_top" TITLE="Pin Files"><U><B>Pin Files</B></U></A><B>   |   </B><A HREF="id24.htm" TARGET="_top" TITLE="Language"><U><B>Language</B></U></A><B>   |   </B><A HREF="id28.htm" TARGET="_top" TITLE="Directory Organization"><U><B>Directory Organization</B></U></A><B>   |   </B><A HREF="id29.htm" TARGET="_top" TITLE="Simulation"><U><B>Simulation</B></U></A><B>   |   </B><A HREF="id30.htm" TARGET="_top" TITLE="Synthesis"><U><B>Synthesis</B></U></A><B>   |   </B><A HREF="id33.htm" TARGET="_top" TITLE="Xilinx Tools"><U><B>Xilinx Tools</B></U></A><B>   |   </B><B>Examples</B></div> <div> </div> </td> </tr><tr> <td valign="top" width=210 BGCOLOR="#FFFFFF" TEXT="#080000"> <div> Examples</div> <div> <B><IMG SRC="05a69830.gif" border=0 width="105" height="131" ALIGN="BOTTOM" HSPACE="0" VSPACE="0"></B><A HREF="http://www.polybus.com" TARGET="_top" TITLE="http://www.polybus.com"><U><B>Polybus</B></U></A></div> <bR> </td> <td valign="top" height=390 BGCOLOR="#FFFFFF" TEXT="#080000"> <div> <B>Verilog Examples</B></div> <div> <A HREF="http://www.polybus.com/hdlmaker/verilog_example/basic.top.html" TARGET="_top" TITLE="http://www.polybus.com/hdlmaker/verilog_"><U>Basic top file</U></A></div> <div> <A HREF="http://www.polybus.com/hdlmaker/verilog_example/basic_connect.top.html" TARGET="_top" TITLE="http://www.polybus.com/hdlmaker/verilog_"><U>Simple connections</U></A></div> <div> <A HREF="http://www.polybus.com/hdlmaker/verilog_example/basic_shuffle.top.html" TARGET="_top" TITLE="http://www.polybus.com/hdlmaker/verilog_"><U>Shuffled connections</U></A></div> <div> <A HREF="http://www.polybus.com/hdlmaker/verilog_example/param.top.html" TARGET="_top" TITLE="http://www.polybus.com/hdlmaker/verilog_"><U>Verilog parameters</U></A></div> <div> <A HREF="http://www.polybus.com/hdlmaker/verilog_example/basic_file.top.html" TARGET="_top" TITLE="http://www.polybus.com/hdlmaker/verilog_"><U>File aliasing</U></A></div> <div> <A HREF="http://www.polybus.com/hdlmaker/verilog_example/loop.top.html" TARGET="_top" TITLE="http://www.polybus.com/hdlmaker/verilog_"><U>Code Generation</U></A></div> <div> <A HREF="http://www.polybus.com/hdlmaker/verilog_example/array_pintest/array_pintest.top.html" TARGET="_top" TITLE="http://www.polybus.com/hdlmaker/verilog_"><U>Virtex Example</U></A></div> <div> <A HREF="http://www.polybus.com/hdlmaker/verilog_example/alu/fplan.top.html" TARGET="_top" TITLE="http://www.polybus.com/hdlmaker/verilog_"><U>Floorplanning Example</U></A></div> <bR> <div> <B>VHDL Examples</B></div> <div> <A HREF="http://www.polybus.com/hdlmaker/vhdl_example/basic.top.html" TARGET="_top" TITLE="http://www.polybus.com/hdlmaker/vhdl_exa"><U>Basic top file</U></A></div> <div> <A HREF="http://www.polybus.com/hdlmaker/vhdl_example/basic_connect.top.html" TARGET="_top" TITLE="http://www.polybus.com/hdlmaker/vhdl_exa"><U>Simple connections</U></A></div> <div> <A HREF="http://www.polybus.com/hdlmaker/vhdl_example/basic_shuffle.top.html" TARGET="_top" TITLE="http://www.polybus.com/hdlmaker/vhdl_exa"><U>Shuffled connections</U></A></div> <div> <A HREF="http://www.polybus.com/hdlmaker/vhdl_example/basic_file.top.html" TARGET="_top" TITLE="http://www.polybus.com/hdlmaker/vhdl_exa"><U>File aliasing</U></A></div> <div> <A HREF="http://www.polybus.com/hdlmaker/vhdl_example/loop.top.html" TARGET="_top" TITLE="http://www.polybus.com/hdlmaker/vhdl_exa"><U>Code Generation</U></A></div> <bR> <bR> </td> </tr></table></body>