HDLmaker generates the Xilinx contraint (.ucf) file which is used to specify pin locations, timing contraints and floor planning constraints. Pin location and timing constraints are taken from the .pin file. Overall timing and floorplanning contraints are specified in the .top file. Here are several examples,

fplan.top

fplan.pin

fplan.v

fplan.ucf

 Xilinx Directives

There are several HDLmaker top file directives which support Xilinx place and route. These are,

#timespec

#timegrp

#tmn_net

#tmn_inst

#tnm_pin

#clock

#fplan