BUFG.job
TOP = BUFG
PART = "xcv800fg680-5"
company = "Polybus Systems Corp, Westford MA"
read -format verilog BUFG.v
uniquify
current_design TOP
remove_constraint -all
compile -map_effort high
report_fpga > BUFG.fpga
report_timing > BUFG.timing
write -format db -hierarchy -output BUFG.db
exit