alu_pattern.v
//-- add_sub.v
//-- Generated by HDLMAKER Rev 5.5.6, Wednesday December 13 2000
//-- Copyright (c) 2000 IKOS Systems, Cupertino, CA
//-- The information contained in this file is confidential and proprietary.
//-- Any reproduction, use or disclosure, in whole or in part, of this
//-- program, including any attempt to obtain a human-readable version of this
//-- program, without the express, prior written consent of IKOS Systems, Cupertino, CA
//-- is strictly prohibited.
//-- Engineer: B. Joshua Rosen
module alu_pattern(
a_data,
b_data,
ce,
done,
error,
gblreset,
mclock,
sub,
sysclk,
y_a,
y_b,
);
//-- IO Declarations
parameter width = 56;
parameter ncols = 12;
parameter position = 0;
parameter run_bit = position+5;
output [width-1:0] a_data;
output [width-1:0] b_data;
reg [width-1:0] a_data;
reg [width-1:0] b_data;
output [ncols-1:0] ce;
reg [ncols-1:0] ce /* synthesis syn_preserve=1 */;
input gblreset;
output [ncols-1:0] sub;
reg [ncols-1:0] sub /* synthesis syn_preserve=1 */;
input sysclk;
input [width-1:0] y_a;
input [width-1:0] y_b;
input [15:5] mclock;
output done;
reg done;
output error;
reg error;
reg run;
//-- Signal Declarations
reg [8:0] a_cntr,b_cntr;
reg [1:0] a_state,b_state;
reg inc_b,inc_c;
reg a_limit,b_limit;
reg ready,err;
reg [6:0] c_cntr;
reg cycle;
reg rst;
reg nxt_reg;
reg [width-1:0] a;
reg [width-1:0] b;
always@(posedge sysclk or posedge gblreset) begin
if(gblreset) begin
run <= 0;
rst <= 1;
a_data <= 0;
b_data <= 0;
end // if (gblreset)
else begin
rst <= mclock[15];
run <= !mclock[15] && mclock[9] && mclock[run_bit];
a_data <= c_cntr[5] ? a : b;
b_data <= c_cntr[5] ? b : a;
end // else: !if(gblreset)
end // always@ (posdege sysclk or posedge gblreset)
always@(posedge sysclk) begin
if(rst) begin
done <= 0;
error <= 0;
end // if (rst)
else begin
if(ready) begin
if(err) error <= 1;
end // if (ready)
if(c_cntr[6]) done <= 1;
end // else: !if(rst)
if(!run) begin
ce <= 0;
a <= 0;
b <= 0;
a_limit <= 0;
b_limit <= 0;
a_cntr <= 0;
b_cntr <= 0;
nxt_reg <= 0;
inc_b <= 0;
ready <= 0;
inc_c <= 1;
err <= 0;
c_cntr <= 0;
cycle <= 0;
sub <= 0;
a_state <= 0;
b_state <= 0;
end // if (!run)
else begin
cycle <= !cycle;
sub <= ~sub;
if(cycle) begin
if(a_limit)
a_cntr <= 0;
else
a_cntr <= a_cntr + 1;
a_limit <= a_cntr == width;
if(a_limit) a_state <= a_state + 1;
a <= a_state[1] ? {a,!a_limit} : {a,a_limit};
inc_b <= a_limit && (a_state == 2'b11);
inc_c <= inc_b && b_limit && (b_state == 2'b11);
if(inc_b) begin
if(b_limit)
b_cntr <= 0;
else
b_cntr <= b_cntr + 1;
b_limit <= b_cntr == width;
if(b_limit) b_state <= b_state + 1;
b <= b_state[1] ? {b,!b_limit} : {b,b_limit};
end // if (a_limit)
if(inc_c) begin
ce <= {ce,ce[ncols-2:0] == 0};
c_cntr <= c_cntr + 1;
end // if (inc_c)
if(ce[0]) ready <= 1;
if(ready) begin
err <= y_a != y_b;
end // if (ready)
end // if (cycle)
end // else: !if(!run)
end // always@ (posedge sysclk)
endmodule