fplan.top
#module "fplan";
#engineer "B. Joshua Rosen";
#company "Polybus Systems, Westford, MA";
#part_type "XCV800";
#family "virtex";
#part_number "Xilinx XCV800fg680";
#package "fg680";
#speed "4";
#revision "1.1";
#date "12/08/00";
#casesensitive;
#timescale "1 ns/100 ps";
#include "internal.pin";
#int i,j,k,next,inst;
#int row,col,blk,num_bits,bit,num_cols,extra,col_limit,num_rows;
#string unit,acc;
#assign col_limit = 10;
#assign num_rows = 56;
#assign num_bits = num_rows * 2;
#print "number of bits: " $ num_bits;
#insert "BUFG.v",
connect I = srcclk,
connect O = sysclk;
#insert "BUFG.v",
connect I = src2x,
connect O = clk_2x;
#insert "CLKDLL.v",
connect CLK0 = srcclk,
connect CLK180 = srcclk_l,
connect CLK270 = clk_a,
connect CLK90 = clk_b,
connect CLKDV = clk_dv,
connect CLK2X = src2x,
connect CLKIN = vclock,
connect CLKFB = sysclk,
connect RST = clkreset,
connect LOCKED = lock;
#insert "BUFG.v",
connect I = tclkin,
connect O = tclk;
#insert "STARTUP_VIRTEX_GSR.v", name = "?glbl",
connect GSR = greset;
#insert "rstbuff.v";
#assign col = first+1;
#assign inst = 1;
#for(j=0;j<4;j++)
{
#assign extra = j >> 1;
#assign num_cols = col_limit + extra;
#for(i=0;i
{
#assign acc = "acc_a" + j;
#assign acc = acc $ "_" $ i;
#insert "add_sub.v",name = "add_sub_",
parameter width = num_bits,
connect a[255:0] = "a_a" + j[255:0],
connect b[255:0] = "b_a" + j[255:0],
connect y[255:0] = "y_a" + j[255:0],
connect acc[255:0] = #acc[255:0],
connect sub = "sub_a" + j[#i],
connect ce = "ce_a" + j[#i],
connect enb = "enb_a" + j[#i];
#assign bit = num_bits - 1;
#for(k=0;k
{
#assign row = k/2;
#assign row++;
#assign unit = "add_sub_" $ inst $ "/acc" $ "[" $ bit $ "]";
#fplan unit ,row,col,slice;
#assign bit--;
}
#assign col+=2;
#assign inst++;
}
#assign next = j + 1;
#if(next == 4)
{
#assign next = 0;
}
#insert "alu_pattern.v",
parameter width = num_bits,
parameter ncols = num_cols,
parameter position = j,
connect a_data[255:0] = "a_a" + j[255:0],
connect b_data[255:0] = "b_a" + j[255:0],
connect ce[255:0] = "ce_a" + j[255:0],
connect done = done[#j],
connect enb[255:0] = "enb_a" + j[255:0],
connect error = error[#j],
connect mclock[15:5] = mclock[15:5],
connect sub[255:0] = "sub_a" + j[255:0],
connect y_a[255:0] = "y_a" + j[255:0],
connect y_b[255:0] = "y_a" + next[255:0];
}
#insert "zeroone.v";
#insert "config_scan.v",
parameter result_width = 32,
parameter done_width = 8,
connect results[31:4] = zero,
connect done[3:0] = done[3:0],
connect done[7:4] = zero,
connect results[3:0] = error[3:0],
;
#insert "assign_num.v",
parameter number = 1,
connect val[15:0] = revision[15:0];
#insert "assign_num.v",
parameter number = id_num,
connect val[15:0] = id[15:0];
}
#library_element "CLKDLL";
#library_element "BUFG";
#library_element "STARTUP_VIRTEX_GSR";
#clock "sysclk" 30;
#clock "tclk" 20;
#maxfan 128;
#fplan "clkdll_1", "dll", 2;
#fplan "bufg_1", "bufg", 2;
#fplan "bufg_2", "bufg", 3;
#fplan "bufg_3", "bufg", 0;
#string tms;
#assign tms = "alu_" $ name $ "_pads_1/scan_tms_iff";
#tnm_inst #tms, "tms_iff" ;
#timespec "tms_iff","FFS",15,1;