fplan_pads.v
//-- fplan_pads.v, Revision 1.1
//-- Modified: 12/08/00
//-- Generated by HDLMAKER Rev 5.6.5, Sunday January 21 2001
//-- Engineer: B. Joshua Rosen
//-- Copyright (c) 2001 Polybus Systems, Westford, MA
//-- The information contained in this file is confidential and proprietary.
//-- Any reproduction, use or disclosure, in whole or in part, of this
//-- program, including any attempt to obtain a human-readable version of this
//-- program, without the express, prior written consent of Polybus Systems, Westford, MA
//-- is strictly prohibited.
module fplan_pads(
clkreset,
clkreset_pin,
error,
error_pin,
gblreset,
mclock,
mclock_pin,
reset,
reset_pin,
scan_tdi,
scan_tdi_pin,
scan_tdo,
scan_tdo_pin,
scan_tms,
scan_tms_pin,
sysclk,
tclk,
tclkin,
tclkin_pin,
vclock,
vclock_pin
);
//-- IO Declarations
output clkreset;
input clkreset_pin;
input [3:0] error;
output [3:0] error_pin;
input gblreset;
output [15:5] mclock;
input [15:5] mclock_pin;
output reset;
input reset_pin;
output scan_tdi;
input scan_tdi_pin;
input scan_tdo;
output scan_tdo_pin;
output scan_tms;
input scan_tms_pin;
input sysclk;
input tclk;
output tclkin;
input tclkin_pin;
output vclock;
input vclock_pin;
//-- Signal Declarations
wire error_000_out;
wire error_001_out;
wire error_002_out;
wire error_003_out;
wire mclock_005_in;
wire mclock_006_in;
wire mclock_007_in;
wire mclock_008_in;
wire mclock_009_in;
wire mclock_010_in;
wire mclock_011_in;
wire mclock_012_in;
wire mclock_013_in;
wire mclock_014_in;
wire mclock_015_in;
wire scan_tms_in;
IBUF clkreset_i(
.I(clkreset_pin),
.O(clkreset)
);
OBUF error_000_o(
.I(error_000_out),
.O(error_pin[000])
);
fdc error_000_off (
.c(sysclk),
.d(error[000]),
.q(error_000_out),
.clr(gblreset)
);
OBUF error_001_o(
.I(error_001_out),
.O(error_pin[001])
);
fdc error_001_off (
.c(sysclk),
.d(error[001]),
.q(error_001_out),
.clr(gblreset)
);
OBUF error_002_o(
.I(error_002_out),
.O(error_pin[002])
);
fdc error_002_off (
.c(sysclk),
.d(error[002]),
.q(error_002_out),
.clr(gblreset)
);
OBUF error_003_o(
.I(error_003_out),
.O(error_pin[003])
);
fdc error_003_off (
.c(sysclk),
.d(error[003]),
.q(error_003_out),
.clr(gblreset)
);
IBUF mclock_005_i(
.I(mclock_pin[005]),
.O(mclock_005_in)
);
fdc mclock_005_iff(
.c(sysclk),
.d(mclock_005_in),
.q(mclock[005]),
.clr(gblreset)
);
IBUF mclock_006_i(
.I(mclock_pin[006]),
.O(mclock_006_in)
);
fdc mclock_006_iff(
.c(sysclk),
.d(mclock_006_in),
.q(mclock[006]),
.clr(gblreset)
);
IBUF mclock_007_i(
.I(mclock_pin[007]),
.O(mclock_007_in)
);
fdc mclock_007_iff(
.c(sysclk),
.d(mclock_007_in),
.q(mclock[007]),
.clr(gblreset)
);
IBUF mclock_008_i(
.I(mclock_pin[008]),
.O(mclock_008_in)
);
fdc mclock_008_iff(
.c(sysclk),
.d(mclock_008_in),
.q(mclock[008]),
.clr(gblreset)
);
IBUF mclock_009_i(
.I(mclock_pin[009]),
.O(mclock_009_in)
);
fdc mclock_009_iff(
.c(sysclk),
.d(mclock_009_in),
.q(mclock[009]),
.clr(gblreset)
);
IBUF mclock_010_i(
.I(mclock_pin[010]),
.O(mclock_010_in)
);
fdc mclock_010_iff(
.c(sysclk),
.d(mclock_010_in),
.q(mclock[010]),
.clr(gblreset)
);
IBUF mclock_011_i(
.I(mclock_pin[011]),
.O(mclock_011_in)
);
fdc mclock_011_iff(
.c(sysclk),
.d(mclock_011_in),
.q(mclock[011]),
.clr(gblreset)
);
IBUF mclock_012_i(
.I(mclock_pin[012]),
.O(mclock_012_in)
);
fdc mclock_012_iff(
.c(sysclk),
.d(mclock_012_in),
.q(mclock[012]),
.clr(gblreset)
);
IBUF mclock_013_i(
.I(mclock_pin[013]),
.O(mclock_013_in)
);
fdc mclock_013_iff(
.c(sysclk),
.d(mclock_013_in),
.q(mclock[013]),
.clr(gblreset)
);
IBUF mclock_014_i(
.I(mclock_pin[014]),
.O(mclock_014_in)
);
fdc mclock_014_iff(
.c(sysclk),
.d(mclock_014_in),
.q(mclock[014]),
.clr(gblreset)
);
IBUF mclock_015_i(
.I(mclock_pin[015]),
.O(mclock_015_in)
);
fdc mclock_015_iff(
.c(sysclk),
.d(mclock_015_in),
.q(mclock[015]),
.clr(gblreset)
);
IBUF reset_i(
.I(reset_pin),
.O(reset)
);
IBUF scan_tdi_i(
.I(scan_tdi_pin),
.O(scan_tdi)
);
OBUF scan_tdo_o(
.I(scan_tdo),
.O(scan_tdo_pin)
);
IBUF scan_tms_i(
.I(scan_tms_pin),
.O(scan_tms_in)
);
fdc scan_tms_iff(
.c(tclk),
.d(scan_tms_in),
.q(scan_tms),
.clr(gblreset)
);
IBUFG tclkin_i(
.I(tclkin_pin),
.O(tclkin)
);
IBUFG vclock_i(
.I(vclock_pin),
.O(vclock)
);
endmodule