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internal.pin

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#uselibrary
#pins
scan_tms        type = in,clk=tclk,pin = at10;
scan_tdo        type = out,c2p=7,pin = at8;
scan_tdi        type = in,p2s=7,pin = at7;
tclkin          type = clkp,pin = aw19;
tclk            type = internal;

mclock[15:5]        type = in,clk=sysclk,pin = [v35,u35,ac35,ab35,ar23,ar22,ar18,ac5,ab5,u5,v5];
vclock          type = clkp,pin = d21;
clkreset        type = in,pin = [e22];
reset           type = in,pin=e23;

sysclk          type = internal;

error[3:0]      type = out,clk=sysclk,pin = [d5,ar4,ah1,ag2];

#endpins
#Summary

    Total Inputs:   17
    Total Outputs:  5
    Total Bidirects:    0
    Total Pins: 22

#endSummary

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HDLMaker Generated Files

internal_pads.v	Verilog file
internal_pads.job	Synopsys script file
internal.pinlist	Pin list sorted by both name and number file
internal.xref	Pin cross reference for PC board models file
internal.prj	Synplicity project file
internal.ucf	Xilinx constraint file file

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