assign_num.job


TOP = assign_num
PART = "xcv800fg680-5"
company = "Polybus Systems Corp, Westford MA"

read -format verilog assign_num.v

uniquify

current_design TOP
remove_constraint -all

compile -map_effort high

report_fpga > assign_num.fpga

report_timing > assign_num.timing

write -format db -hierarchy -output assign_num.db
exit



HDLMaker Generated Files