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basic_connect.top

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#module "basic_connect";

#include "basic.pin";

#insert "dregce32.v",
      connect q[31:0]                         = reg_a[31:0];

#insert "dregce32.v",
      connect d[31:0]                         = reg_a[31:0],
      connect q[31:0]                         = reg_b[31:0];

#insert "dregce32.v",
      connect d[31:0]                         = reg_b[31:0];


#clock "sysclk" 25;

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HDLMaker Generated Files

basic_connect.v	Verilog file
basic_connect.job	Synopsis script file
basic_connect.errors	DRC Error file

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