loop.top


#module "loop";

#include "
loop.pin";

#int i;
#string reg;


#insert "
dregce32.v",
      connect ce                    = ce[0],
      connect q[31:0]                         = reg_a[31:0];

#assign reg = "reg_a";

#for(i=0;i<2;i++)
{
      #insert "
dregce32.v",
            connect ce                      = ce[#i+1],
            connect d[31:0]                 = "reg_a" + i[31:0],
            connect q[31:0]                 = "reg_b" + i[31:0];
      #assign reg++;
}

#insert "
dregce32.v",
      connect ce                              = ce[#i+1],
      connect d[31:0]                         = #reg[31:0];

#clock "sysclk" 25;




HDLMaker Generated Files
loop.v Verilog file
loop.job Synopsis script file
loop.errors DRC Error file