---

param.top

---

#module "param";

#include "basic.pin";

#insert "dregce.v",
      parameter WIDTH = 32,
      connect q[31:0]                         = reg_a[31:0];

#insert "dregce.v",
      parameter WIDTH = 16,
      connect d[15:0]                         = reg_a[15:0],
      connect q[15:0]                         = q[15:0];

#insert "dregce.v",
      parameter WIDTH = 16,
      connect d[15:0]                         = reg_a[31:16],
      connect q[15:0]                         = q[31:16];


#clock "sysclk" 25;

---

HDLMaker Generated Files

param.v	Verilog file
param.job	Synopsis script file
param.errors	DRC Error file

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