---

pintest.top

---

#module "pintest";
#family "virtex";

#include "pintest.pin";


#insert "delay128.top",
    connect ce                              = ce[0],
    connect d                               = d[0],
    connect gblreset                        = gblreset,
    connect q                               = q[0],
    connect sysclk                          = sysclk;

#insert "delay128.top",
    connect ce                              = ce[1],
    connect d                               = d[1],
    connect gblreset                        = gblreset,
    connect q                               = q[1],
    connect sysclk                          = sysclk;

#insert "listener.v";

---

HDLMaker Generated Files

pintest.v	Verilog file
pintest.job	Synopsys script file
pintest.prj	Synplicity Project file
pintest.ucf	Xilinx constraint file
pintest.Make	Synopsy Make file
pintest_v.cmd	Leapfrog Make file
pintest_mt.do	Model Tech script file
pintest_batch.Make	Synopsis batch Make file
pintest.errors	DRC Error file

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