pintest_kernel.job
TOP = pintest_kernel
PART = "xcv800fg680-5"
read -format verilog pintest_kernel.v
elaborate TOP
uniquify
current_design TOP
remove_constraint -all
compile -map_effort high
disconnect_net gblreset -all
report_fpga > pintest_kernel.fpga
report_timing > pintest_kernel.timing
write -format db -hierarchy -output pintest_kernel.db
replace_fpga
set_attribute pintest_kernel "part" -type string "xcv800fg680-5"
write -format edif -hierarchy -output pintest_kernel.sedif
ungroup -all
write_script > pintest_kernel.dc
exit