zeroone.job


TOP = zeroone
PART = "xcv800fg680-5"
company = "Polybus Systems Corp, Westford MA"

read -format verilog zeroone.v

uniquify

current_design TOP
remove_constraint -all

compile -map_effort high

report_fpga > zeroone.fpga

report_timing > zeroone.timing

write -format db -hierarchy -output zeroone.db
exit



HDLMaker Generated Files