accblock.job
TOP = accblock
PART = "4013epq240-3"
read -format vhdl acc46.vhd
read -format vhdl accblock.vhd
elaborate TOP
uniquify
current_design TOP
remove_constraint -all
compile -map_effort high
disconnect_net gblreset -all
report_fpga > accblock.fpga
report_timing > accblock.timing
write -format db -hierarchy -output accblock.db
replace_fpga
set_attribute accblock "part" -type string "4013epq240-3"
set_attribute find(design,"*") "xnfout_write_map_symbols" -type boolean FALSE
write -format xnf -hierarchy -output accblock.sxnf
ungroup -all
write_script > accblock.dc
exit