sample_pads.job
TOP = sample_pads
PART = "4013epq240-3"
read -format vhdl sample_pads.vhd
uniquify
current_design TOP
remove_constraint -all
compile -map_effort high
report_fpga > sample_pads.fpga
report_timing > sample_pads.timing
write -format db -hierarchy -output sample_pads.db
exit