Pin File

Pin files are used to specify the pins of a module or entity. Pin files are used for both the top level of the design and for all of the intermediate levels.

Here are some examples:

1. sample.pin is a top level design, HDLmaker generates a pad ring called sample_pads.vhd or sample_pads.v, as well as the entitiy or module section for the design.
2. accblock.pin is an intermediate level pin file. It is used to generate entity and module blocks, but no pad ring.

Pin file statement types are restrictions

1. Titles
2. RCS Revision
3. Use library
4. No pad ring
5. Signal name formats
6. Default signal names
7. Clocks
8. Clock enables
9. Tristates
10. Pullups/Pulldown resistors
11. Output slew rates and input setups
12. Pin numbers
13. Aliases
14. Xilinx timing constraints

#title and #module

The file must contain a #title statement and a #module statement. These must both specify the same file name.

#title "file_name"

#module "file_name"

#revision

The #revision statement is optional. It is used for the RCS revision header.

#uselibrary

The #uselibrary is highly recommended for PAD rings. It causes hdlmaker to use Xilinx 4000/5200 or Lucent ORCA IO cells directly instead of writing pure VHDL.

Synopsys does much better if it is told what to do.

#nopadring

Is used for intermediate level modules.

Signal name formats:

The legal characters for signal names are a-z,0-9 and _. If the signal refers to a bus or

bus fragment then the format is signal_name[#] or signal_name[#..#] where .. represents a

range. Examples of legal names are

foo

foo_bar[3]

myname[8..15]

yourname[31..0]

The following name is illegal because the name portion of the string contains a number.

name12[15..19]

Default signal names.

For bidirectional IOs hdlmaker has the following conventions

name Internal source name

fb_name Feedback signal from the IO pin

name_pin Name of pin.

For all unidirectional pins

name Internal signal name

name_pin Pin name

Type field:

The type field specifies the direction of the pin. The available types are

in input

out output

inout bidirectional or tristate

rsvd reserved (used to preserve a pin number for future use)

clks Xilinx secondary clock buffer

clkp Xilinx primary clock buffer

tdo Xilinx 4000 tdo buffer (for 5200 or ORCA use a regular out)

internal Internal control signal (for example clock enables or tristate enables)

clk,inclk,outclk,lch:

The clk statement specfies the clk to the IO registers.

clk=sysclk positive edge triggered clock

clk=!sysclk negative edge triggered clock

lch=sysclk High true latch enable (inputs only)

lch=!sysclk Low true latch enable(inputs only)

inclk=sysclk positive edge triggered input clock

inclk=!sysclk negative edge triggered input clock

outclk=sysclk positive edge triggered output clock

outclk=!sysclk negative edge triggered output clock

If no clk statement is present then the IO pin is assumed to be combinatorial

inclkenb,outclkenb,ioclkenb:

Input and output clock enables are specified as follows:

inclkenb=enb_name Input flipflop enable

outclkenb=enb_name Output enable

inoutenb=enb_name Both

tristate

The tristate enable is high = disable, low = enable. The tristate statement has the form:

tristate=!enable Enable the output of enable is high

tristate=enable_l Enable the output if enable_l is low

resetlevel

The default reset level is 0. If a preset is desired then use

resetlevel=1

resistor

Pullup and pulldown resistors ,may be specified as follows:

resistor=pullup

resistor=pulldown

speed,setup

The speed of the outputs and hold time characteristics of the inputs may be controled as follows:

speed=slow Use the slew limited output buffers, default is the fast buffers

speed=fast Use the fast output buffers, default is the fast buffers

setup=nodelay Use the fast input buffers, some hold time will be required.

setup=nohold Use the slow input buffers, hold time is 0, setup time is much longer

p2s,c2p

Xilinx timing constraints.

p2s=16 The pin to setup time of this pin is 16 ns.

c2p=20 The clock to pin time of this pin is 20 ns.

alias:

The alias statement is used to provide an additional connection to a pin. Xilinx inputs can

be both registered and combinatorial at the same time. An example is shown below:

txbusy type = in,clk = sysclk,pin=128,resetlevel=1;

nxttxbusy type = in,alias = txbusy,p2s=16 ;

txbusy is registered,nxttxbusy is combinatorial.

pin

The pin statement specifies the pin numbers. The pin list is an arbitrary list of numbers.

Examples:

pin=12

pin=[0..3,8,31..20,7]

ranges can be either high to low or low to high and can be mixed in a single list. The pin

numbers are matched to the bus pins from left to right.