Polybus Systems offers a customizable set of FPGA test patterns for all Xilinx FPGAs. The suite consists of over 400 patterns which test the internal functionality and interconnect of any Xilinx FPGA. The tests help eliminate FPGAs that have failed due to handling problems and infant mortality. In addition the patterns provided a greatly enhanced level of testing which helps assure the future upgradability of FPGA based systems.

The test patterns may be run in system or on a chip tester to provide a greater level of screening.

 Why Do In System Testing?
In system testing can provide a much higher level of coverage then manufacturer screening. Manufacturer tests, run on a chip tester, are limited to a handful of patterns and a total test time that can be a few seconds at most. In system tests have no such limitations. The Polybus test suite consists of over 400 patterns and the test time can be anywhere from five minutes to many hours (when used for system burn in).

 How Effective Are The Polybus FPGA Test Patterns?
FPGAs present a unique testing problem. FPGAs have hugely complicated interconnect networks that can be connected in a nearly infinite number of ways. As such it is theoretically impossible to test every possible pathway. Manufacturer's tests attempt to test each individual switch but they can't test every interconnect path. Testing every switch will eliminate parts with major defects but it can't find every problem. Polybus' test suite has been designed to test a much wider range of interconnect patterns. While Polybus can not claim that it's test suite can provide 100% coverage, as stated earlier that's theoretically impossible, customer experience has shown that in system testing with Polybus' test patterns can reduce the probability of shipping a defective part by up to two orders of magnitude.

 How Common Are FPGA Defects?
Polybus has produced in system test patterns for seven generations of Xilinx FPGAs. Over that time the FPGA defect rate has been fairly constant, ranging between 1% and 3%.

 How Serious Are FPGA Defects?
Defects are typically small, generally effecting about one in fifty patterns, that is if fifty different patterns are loaded into the defective FPGA forty nine will work correctly and one will work incorrectly. For a system that consists of a single FPGA and a single programming pattern the probability of a FPGA caused failure is small, typically between 1 in 2500 and 1 in 10000 systems. For systems with a single dynamically loaded FPGA the probability of an FPGA caused failure approaches 1 in 50 as the number of different programming patterns is increased. For systems with large numbers of FPGAs the probability of a FPGA caused failure also increases.

 What Type Of System Needs In System FPGA Testing?
Any system that supports field upgradable FPGA pattern's benefits tremendously if the FPGAs are tested with Polybus' in system test patterns. Every time the FPGA pattern is changed you run the risk that the new pattern won't work even though the FPGA worked perfectly with the old pattern. Supplemental screening with Polybus' test patterns significantly reduce the risk that a field upgrade will cause a previously working system to stop functioning.

Any system where maximum reliability is required can also benefit from the Polybus FPGA test suite. Even systems where in circuit testing is impossible, i.e. serial prom based systems, can benefit by doing an additional prescreen on a chip tester.

 Interface Requirements
The interface is customized for the target system. Interface requirements are simple, consisting of a reset, a run signal, a done signal and an error signal. The interface can use a few dedicated pins, a JTAG scan chain, or a custom scan chain as determined by the needs of the target system. In addition to in system tests the Polybus Test Patterns have also been used on chip testers to provide a higher level of prescreening then the standard Xilinx test patterns alone.

 What Sort of Customization Is Available?
Polybus is prepared to provide any sort of interface that the system designer may require. Customization may be as simple as a custom pinout or as complicated as a user defined scan chain. In addition, Polybus can provide in system IO tests in addition to the standard suite of internal tests.  By their very nature IO tests are system specific and as such must be customized for each system.

 Test Coverage
Block RAM
Tristate Buffers
LUT Logic
F5 Mux
F6 Mux
F7 an F8 Muxes (Virtex2 only)
Carry Logic
Multipliers (Virtex2 Only)
Shift Registers
Extensive Interconnect Coverage (North,South,East,West,NE,NW,SE,SW, multiple strides)

 Further Information
For further information and pricing please contact

Joshua Rosen bjrosen@Polybus.com
978 828-0944