pintest_ctrl.v
//-- pintest_ctrl.v
//-- Generated by HDLMAKER Rev 5.4.6, Thursday September 21 2000
//-- The information contained in this file is confidential and proprietary.
//-- Any reproduction, use or disclosure, in whole or in part, of this
//-- program, including any attempt to obtain a human-readable version of this
//-- program, without the express, prior written consent of Polybus Systems, Westford MA
//-- is strictly prohibited.
//-- Engineer: B. Joshua Rosen
// The command register is used to control the special bits, each bit has a two bit field
// 00 Normal operation
// 01 Clocked during cycle 0, normal during other cycles
// 10 Enabled during cycle 0 and during it's own cycle, logic level 0
// 11 Enabled during cycle 0 and during it's own cycle, logic level 1
module pintest_ctrl(
chip,
cmd_op,
cntr,
data,
done,
dump_addr,
dump_data,
dump_enb,
dump_wrt,
clr_parity,
load_parity,
sel_parity,
gblreset,
init,
mclock,
ram_d,
ram_in,
ram_out,
sample,
scan_in,
scan_out,
scan_addr,
scan_wrt,
scan_enb,
special,
enb_special_l,
init_val,
sysclk,
tclk,
enb_data_l,
enb_external_io_l
);
//-- IO Declarations
input [15:0] chip;
input [31:0] cmd_op;
output [487:0] data;
reg [487:0] data /* synthesis syn_preserve=1 */ ;
output done;
output [7:0] dump_addr;
reg [7:0] dump_addr;
output [1:0] dump_data;
reg [1:0] dump_data;
output dump_enb;
reg dump_enb;
output dump_wrt;
reg dump_wrt;
output sel_parity;
reg sel_parity;
output [1:0] load_parity;
reg [1:0] load_parity;
output clr_parity;
reg clr_parity;
input gblreset;
output init;
reg init;
input [15:5] mclock;
output [255:247] ram_d;
output sample;
reg sample;
input scan_in;
output scan_out;
output [11:0] scan_addr;
reg [11:0] scan_addr;
output scan_wrt;
reg scan_wrt;
input sysclk;
output [471:0] enb_data_l;
reg [471:0] enb_data_l /* synthesis syn_preserve=1 */;
output [15:0] enb_external_io_l;
reg [15:0] enb_external_io_l;
input tclk;
output [15:0] ram_in;
reg [15:0] ram_in;
input [15:0] ram_out;
input scan_enb;
output [5:0] special;
output [5:0] enb_special_l;
reg [5:0] special;
reg [5:0] enb_special_l;
output [26:0] cntr;
reg [26:0] cntr;
output [1:0] init_val;
reg [1:0] init_val;
//-- Signal Declarations
reg [495:0] enb_data;
reg sync_reset;
reg run;
reg [1:0] start;
reg [1:0] dump_start;
reg [4:0] dump_ctrl;
reg pattern;
reg data_src;
reg clk_src;
reg its_me;
reg [15:0] scan_reg;
reg [3:0] scan_cnt;
reg [1:0] dump_ce;
reg [2:0] dump_q;
reg [1:0] dump_run;
wire [0:63] bitstream;
reg [7:0] init_cntr;
reg [1:0] init_start;
reg [8:0] dump_cntr;
reg [1:0] enb_stb;
reg enb_special;
reg next_chip;
reg scan_ld;
reg enb_extern;
assign bitstream = {40'h00AA123789,cntr[25:6],5'h0};
assign ram_d = 0;
assign scan_out = scan_reg[0];
always @(posedge tclk) begin
if(!scan_enb) begin
ram_in <= 0;
scan_cnt <= 0;
scan_wrt <= 0;
scan_addr <= 0;
scan_reg <= 16'hBABE;
scan_ld <= 0;
end // if (gblreset)
else begin
scan_cnt <= scan_cnt + 1;
ram_in <= {scan_in,ram_in[15:1]};
scan_ld <= scan_cnt == 14;
scan_wrt <= scan_ld;
if(scan_ld) begin
scan_reg <= ram_out;
end // if (scan_ld)
else begin
scan_reg <= scan_reg >> 1;
end // else: !if(scan_wrt)
if(scan_wrt) begin
scan_addr <= scan_addr + 1;
end // if (scan_wrt)
end // else: !if(gblreset)
end // always @ (posedge tclk or posedge gblreset)
assign done = cntr[26];
always @(posedge sysclk or posedge gblreset) begin
if(gblreset) begin
sync_reset <= 1;
init <= 0;
init_val <= 0;
init_cntr <= 0;
init_start <= 0;
enb_special_l[0] <= 1;
enb_special_l[1] <= 1;
enb_special_l[2] <= 1;
enb_special_l[3] <= 1;
enb_special_l[4] <= 1;
enb_special_l[5] <= 1;
special[0] <= 0;
special[1] <= 0;
special[2] <= 0;
special[3] <= 0;
special[4] <= 0;
special[5] <= 0;
enb_data_l <= ~472'h0;
enb_external_io_l <= ~16'h0;
enb_extern <= 0;
data <= 0;
end // always @ (posedge sysclk or posedge gblreset)
else begin
sync_reset <= mclock[15];
init_start <= {init_start,sync_reset};
if(init_start == 2'b01) begin
init_cntr <= 1;
init <= 1;
end // if (sync_reset)
else if(init) begin
init_cntr <= init_cntr + 1;
init <= init_cntr != 0;
end // if (init)
init_val <= cmd_op[31:30];
enb_data_l <= ~enb_data[473:2];
enb_extern <= cmd_op[16];
enb_external_io_l <= enb_extern ? ~enb_data[489:474] : 16'hFFFF;
data <= {488{data_src}};
enb_special_l[0] <= special_enb(enb_data[490],enb_special,cmd_op[1:0]);
enb_special_l[1] <= special_enb(enb_data[491],enb_special,cmd_op[3:2]);
enb_special_l[2] <= special_enb(enb_data[492],enb_special,cmd_op[5:4]);
enb_special_l[3] <= special_enb(enb_data[493],enb_special,cmd_op[7:6]);
enb_special_l[4] <= special_enb(enb_data[494],enb_special,cmd_op[9:8]);
enb_special_l[5] <= special_enb(enb_data[495],enb_special,cmd_op[11:10]);
special[0] <= special_bit(enb_data[490],data_src,clk_src,cmd_op[1:0]);
special[1] <= special_bit(enb_data[491],data_src,clk_src,cmd_op[3:2]);
special[2] <= special_bit(enb_data[492],data_src,clk_src,cmd_op[5:4]);
special[3] <= special_bit(enb_data[493],data_src,clk_src,cmd_op[7:6]);
special[4] <= special_bit(enb_data[494],data_src,clk_src,cmd_op[9:8]);
special[5] <= special_bit(enb_data[495],data_src,clk_src,cmd_op[11:10]);
end // else: !if(gblreset)
end // always @ (posedge sysclk or posedge gblreset)
always@(posedge sysclk) begin
if(dump_run[0])
dump_cntr <= dump_cntr + 1;
else
dump_cntr <= 0;
if(dump_wrt)
dump_addr <= dump_addr + 1;
else
dump_addr <= 0;
end // always@ (posedge sysclk)
always@(posedge sysclk) begin
if(sync_reset) begin
cntr <= 0;
run <= 0;
start <= 0;
enb_data <= 0;
sample <= 0;
dump_start <= 0;
dump_enb <= 1;
dump_wrt <= 1;
dump_data <= 0;
dump_ctrl <= 0;
pattern <= 0;
data_src <= 0;
its_me <= 0;
sel_parity <= 0;
load_parity <= 0;
dump_ce <= 0;
dump_q <= 0;
dump_run <= 0;
clk_src <= 0;
clr_parity <= 1;
enb_stb <= 0;
enb_special <= 0;
next_chip <= 0;
end // if (gblreset)
else begin
sample <= mclock[12] & !dump_run;
start <= {start,mclock[9]};
dump_start <= {dump_start,mclock[14]};
clr_parity <= dump_start == 2'b01;
if((dump_cntr == 9'h101))
dump_run[0] <= 0;
else if(dump_start == 2'b01)
dump_run[0] <= 1;
dump_run[1] <= dump_run[0];
dump_data[0] <= dump_run[0] & ~dump_cntr[0];
dump_data[1] <= dump_run[1] & dump_cntr[0];
dump_ce <= dump_run & dump_data;
dump_q <= {dump_q,dump_ce != 0};
load_parity <= dump_ce;
dump_wrt <= dump_q[2] & dump_q[0];
dump_enb <= dump_q[2] & dump_q[0];
sel_parity <= ((dump_addr == 252) || (dump_addr == 253));
if(start == 2'b01)
run <= 1;
else if(done)
run <= 0;
if(enb_data[0])
clk_src <= !clk_src;
else
clk_src <= 0;
if(run) begin
cntr <= cntr + 1;
// cntr[7:0] <= cntr[7:0] + 1;
// if(cntr[7:0] == 8'hFF) begin
// if(cntr[14:8] == 7'h7F) begin
// cntr[26:8] <= cntr[26:8] + 1;
// end // if (cntr[14:8] == 7'h7F)
// else begin
// cntr[14:8] <= 7'h7F;
// end // else: !if(cntr[14:8] == 7'h7F)
// end // if (cntr[7:0] == 10'h3FF)
end // if (run)
pattern <= bitstream[cntr[5:0]];
data_src <= pattern;
next_chip <= cntr[14:0] == 1;
if(next_chip && (cntr[25:15] == chip[10:0]))
its_me <= 1;
else if(enb_data[0])
its_me <= 0;
enb_stb <= {enb_stb,cntr[5:0] == 60};
if(enb_stb[1]) begin
if(its_me) begin
enb_data <= 1;
enb_special <= !cmd_op[29];
end // if (its_me)
else begin
enb_special <= 0;
enb_data[1:0] <= {enb_data[0],1'b0};
enb_data[2] <= enb_data[1] & !cmd_op[29];
enb_data[495:3] <= enb_data[494:2];
end // else: !if(its_me)
end // if (cntr[5:0] == 62)
end // else: !if(gblreset)
end // always@ (posedge sysclk or posedge gblreset)
function special_bit;
input enb;
input din;
input cin;
input [1:0] cmd;
begin
casex({enb,cmd})
3'b1xx: special_bit = din;
3'b000: special_bit = din;
3'b001: special_bit = cin;
3'b010: special_bit = 0;
3'b011: special_bit = 1;
endcase // casex({enb,cmd})
end
endfunction // special_bit
function special_enb;
input enb;
input enb_1st;
input [1:0] cmd;
begin
casex(cmd)
2'b00: special_enb = !enb;
2'b01: special_enb = !(enb | enb_1st);
2'b1x: special_enb = 0;
endcase // casex({enb,cmd})
end
endfunction // special_enb
endmodule