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Topfiles

Top files are the glue that holds an HDLmaker design together. Top files are used to specify the following things:

Module name
FPGA type, package and speed
Work library
Include files
Component instances
Synopsys directives
Xilinx directives
Verilog XL directives
Synplicity directives

Here are some examples

sample.top is an example of the top level of a design. HDLmaker generates either a VHDL file, sample.vhd, or a Verilog file, sample.v, depending on the HDLMAKER_LANGUAGE variable.
accblock.top is an example of a lower level of the design.

Module name

Specifies the name of the module, should be the same as then name in the .pin file.

#module "file_name";

FPGA part type, package and speed

Part types, packages and speeds are specified as follows:

#part_type "4013E";
#package "pq240";
#speed "-3";

Working directory

The directory statement is used to specify the work library for the VHDL configuration.

Include files

#include

Directly includes the text of the file. If the file is a .pin file then the pad ring and

entity declarations are automaticcaly generated. A #include of a pin file is required.

#include "file_name.pin";

Inserting component instances

#insert: is used to insert an instance of a component. The extension specifies the source type.

#insert "foo.top"; Generates a VHDL or Verilog file from the .top file and inserts it.

#insert "foobar.vhd"; Insert a VHDL component. The entity definition is taken from the file of the same name.

#insert "example.abl"; Executes ABEL, converts the results to VHDL or Verilog and then inserts it.

#insert "bar.v"; Insert a verilog component taken from the file of the same name.

The default signal name that is attached to a pin has the same name as the pin. If a different name is required this can be accomplished with a connection file. For example

#insert "corepath.top",connections="acch.conn";

The format for a connection file is shown below:

#connect d[11..0] = input_bus[11..0];

#connect gblreset = gblreset;

#connect q[11..0] = reg_results[11..0];

#connect sysclk = sysclk;

A default .conn file is automatically generated for each component called by a

.top file. The simple way to make a .conn file is to run hdlmaker once and then

edit the resulting .conn files.

Multiple instances of a component usually require a connection file. It is also a good idea when instantiating a top file component to only specify .top for the first instance and to use .v or .vhd for the remaining instances. For example:

#insert "accblock.top",connections="block1.conn"; #insert "accblock.vhd",connections="block2.conn";

Synopsys Directives

#clock

#clock tells Synopsis that a particular signal is a clock. The example below

specifies that sysclk_pin is a 40 ns clock. The _pin at the name is there because

hdlmaker names all external pin signals name_pin.

#clock "sysclk_pin" 40;

#dont_touch

This is a Synopsis directive that tells it not to remove a component even though it's outputs aren't connected. A dont_touch is required for the startup (reset) block. It is also required for IO buffers. However hdlmaker takes care of IO buffers itself so you don't have to do anything for those.

#dont_touch "startup_1";

#no_timespecs

Stop Synopsys from emitting time specs in the SXNF files. #no_timespecs is the same as

#synopsys "xnfout_constraints_per_endpoint = 0"

#input_setup

Specify an input setup constraint to Synopsys

#input_setup "pin_name" "clock_name" 20;

This is equivalent to:

#synopsys "set_input_delay -clock clock_name -max 20 pin_name";

#input_hold

Specify an input hold constraint to Synopsys

#input_hold "pin_name" "clock_name" 20;

This is equivalent to:

#synopsys "set_input_delay -clock clock_name -min 20 pin_name";

#boundary_optimization

Enables some logic optimization across hierarchical boundaries. #flatten takes precedence

over #boundary_optimization.

#flatten

Forces Synopsys to flatten the design

#synopsys

This allows you to add arbitrary commands to the Synopsys .job file

#synopsys "xnfout_constraints_per_endpoints = 0"

Xilinx directives

#timespec,#timegrp

These are Xilinx timespec directives. The example shown below specifies that the

clock to RAM setup is 30 ns.

#timespec="FROM:FFS:TO:RAMS=30";

#locate

Insert placement constraints into the appropriate constraint file (.cst file for the

old ppr Xilinx tool, .pcf file for the new Xilinx place and route tool).

#locate "fdc_1","clb_r1c1";

#priority

Insert a prioritize command to PAR into the pcf file. Prioritize is used to up the

priority of a signal to the place and route software.

#priority "rxvalid" 90;

Valid priority levels run from 1 to 99 (highest priority). The default priority is 3.

Verilog XL directives

#timescale

Insert Verilog `timescale command

#timescale "1 ns/1 ps";

Inserts the following

`timescale 1 ns/1 ps

#uselib

Insert Verilog uselib command

#uselib "/tools/xilinx/xact-5.2.1-verilog/verilog4000e";

Inserts the following

`uselib dir=/tools/xilinx/xact-5.2.1-verilog/verilog4000e libext=.v

Synplicity Directives

The following are Synplicity directives, not required unless you are using Synplicity

#maxfan

Specifies the maximum fanout

#maxfan "16";

#black_box

This is a Synplicity directive. It is similiar to the Synopsys #dont_touch command.

Hdlmaker also uses the black_box directive to exclude modules from Synopsys Make

files.

#black_box "startup";

ABEL Conversions

Hdlmaker converts ABEL to VHDL by translating the .eqn and .tt1 output files from ABEL.

The script hdlmaker_lib/csh/runabl is used by hdlmaker to invoke ABEL.

This script must be modified for your environment. This script does the following:

runs ABEL

copies the .eqn and .tt1 result files into the local directory

If the ABEL source file has pin numbers then an .xref file will automatically be generated. PADs netlists that include ABEL based PLDs will be converted into VHDL. An attribute called "pldfile" which references the .abl file must be attached to each PLD.