Download & Installation

<body topmargin=0 leftmargin=0 marginheight=0 marginwidth=0> <table cellpadding=0 cellspacing=0 border=0><tr> <td valign="top" colspan=2 height=90 BGCOLOR="#CC9900" TEXT="#080000" bgproperties="fixed" background="045005a0dwnjzk.gif"> <div> <A HREF="index.htm" TARGET="_top" TITLE="HDLmaker"><U><B>home</B></U></A><B>     | </B><B> </B><B> </B><B>  </B><FONT SIZE="5" COLOR="#FFCC66" FACE="Arial" ><B>HDLmaker</B></FONT></div> <div> <B>Download & Installation</B><B>   |   </B><A HREF="id18.htm" TARGET="_top" TITLE="Running HDLmaker"><U><B>Running HDLmaker</B></U></A><B>   |   </B><A HREF="id20.htm" TARGET="_top" TITLE="Users Manual"><U><B>Users Manual</B></U></A><B>   |   </B><A HREF="id27.htm" TARGET="_top" TITLE="License"><U><B>License</B></U></A><B>   |   </B><A HREF="id19.htm" TARGET="_top" TITLE="Contact Us"><U><B>Contact Us</B></U></A><B>   |   </B><A HREF="id31.htm" TARGET="_top" TITLE="Help"><U><B>Help</B></U></A></div> <div> </div> </td> </tr><tr> <td valign="top" width=210 BGCOLOR="#FFFFFF" TEXT="#080000"> <div> Download & Installation</div> <div> <B><IMG SRC="05d69830.gif" border=0 width="105" height="131" ALIGN="BOTTOM" HSPACE="0" VSPACE="0"></B><A HREF="http://www.polybus.com" TARGET="_top" TITLE="http://www.polybus.com"><U><B>Polybus</B></U></A></div> <bR> <bR> <div> <A HREF="id17_m.htm#download_software" TARGET="TRLX_Middle" TITLE="Download Installation"><U><B>Download</B></U></A></div> <div> <A HREF="id17_m.htm#installing_software" TARGET="TRLX_Middle" TITLE="Download Installation"><U><B>Install</B></U></A></div> <div> <A HREF="id17_m.htm#installing_the_man_page" TARGET="TRLX_Middle" TITLE="Download Installation"><U><B>Installing the Man Page</B></U></A></div> <div> <A HREF="id17_m.htm#making_and_installing_hdlmaker" TARGET="TRLX_Middle" TITLE="Download Installation"><U><B>Making and installing HDLmaker</B></U></A></div> <div> <A HREF="id17_m.htm#setting_up_paths" TARGET="TRLX_Middle" TITLE="Download Installation"><U><B>Setting up paths</B></U></A></div> <div> <A HREF="id17_m.htm#setting_up__cshrc_files" TARGET="TRLX_Middle" TITLE="Download Installation"><U><B>Setting up .cshrc files</B></U></A></div> <div> <A HREF="id17_m.htm#setting_up__bashrc_files" TARGET="TRLX_Middle" TITLE="Download Installation"><U><B>Setting up .bashrc files</B></U></A></div> <bR> <div> <A HREF="id17_m.htm#environment_variables" TARGET="TRLX_Middle" TITLE="Download Installation"><U><B>Required Env Variables</B></U></A></div> <div> <A HREF="id17_m.htm#hdlmaker_lib" TARGET="TRLX_Middle" TITLE="Download Installation"><U><B>hdlmaker_lib</B></U></A></div> <div> <A HREF="id17_m.htm#hdlmaker_language" TARGET="TRLX_Middle" TITLE="Download Installation"><U><B>hdlmaker_language</B></U></A></div> <bR> <div> <A HREF="id17_m.htm#optional_environment_variables" TARGET="TRLX_Middle" TITLE="Download Installation"><U><B>Optional Env Variables</B></U></A></div> <div> <A HREF="id17_m.htm#hdlmaker_company" TARGET="TRLX_Middle" TITLE="Download Installation"><U><B>hdlmaker_company</B></U></A></div> <div> <A HREF="id17_m.htm#hdlmaker_engineer" TARGET="TRLX_Middle" TITLE="Download Installation"><U><B>hdlmaker_engineer</B></U></A></div> <div> <A HREF="id17_m.htm#hdlmaker_copyright" TARGET="TRLX_Middle" TITLE="Download Installation"><U><B>hdlmaker_copyright</B></U></A></div> <div> <A HREF="id17_m.htm#hdlmaker_case_sens" TARGET="TRLX_Middle" TITLE="Download Installation"><U><B>hdlmaker_case_sens</B></U></A></div> <div> <A HREF="id17_m.htm#hdlmaker_synthesis" TARGET="TRLX_Middle" TITLE="Download Installation"><U><B>hdlmaker_synthesis</B></U></A></div> <div> <A HREF="id17_m.htm#hdlmaker_simulator" TARGET="TRLX_Middle" TITLE="Download Installation"><U><B>hdlmaker_simulator</B></U></A></div> <div> <A HREF="id17_m.htm#hdlmaker_verilog_cmd" TARGET="TRLX_Middle" TITLE="Download Installation"><U><B>hdlmaker_verilog_cmd</B></U></A></div> <div> <A HREF="id17_m.htm#hdlmaker_family" TARGET="TRLX_Middle" TITLE="Download Installation"><U><B>hdlmaker_family</B></U></A></div> <div> <A HREF="id17_m.htm#hdlmaker_map_effort" TARGET="TRLX_Middle" TITLE="Download Installation"><U><B>HDLMAKER_MAP_EFFORT</B></U></A></div> <div> <A HREF="id17_m.htm#hdlmaker_upcase_io" TARGET="TRLX_Middle" TITLE="Download Installation"><U><B>hdlmaker_upcase_io</B></U></A></div> <div> <A HREF="id17_m.htm#schematic_layout" TARGET="TRLX_Middle" TITLE="Download Installation"><U><B>Schematic Env Variables</B></U></A></div> <div> <A HREF="id17_m.htm#hdlmaker_set_defparam" TARGET="TRLX_Middle" TITLE="Download Installation"><U><B>hdlmaker_set_defparam</B></U></A></div> <div> <A HREF="id17_m.htm#hdlmaker_local_copy" TARGET="TRLX_Middle" TITLE="Download Installation"><U><B>HDLMAKER_LOCAL_COPY</B></U></A></div> <div> <A HREF="id17_m.htm#hdlmaker_use_sub_dir" TARGET="TRLX_Middle" TITLE="Download Installation"><U><B>HDLMAKER_USE_SUB_DIR</B></U></A></div> <div> <A HREF="id17_m.htm#hdlmaker_gen_date" TARGET="TRLX_Middle" TITLE="Download Installation"><U><B>HDLMAKER_GEN_DATE</B></U></A></div> <div> <A HREF="id17_m.htm#hdlmaker_allow_sub" TARGET="TRLX_Middle" TITLE="Download Installation"><U><B>HDLMAKER_ALLOW_SUB</B></U></A></div> <div> <A HREF="id17_m.htm#hdlmaker_cshrc" TARGET="TRLX_Middle" TITLE="Download Installation"><U><B>hdlmaker.cshrc</B></U></A></div> <div> <A HREF="id17_m.htm#hdlmaker_sh" TARGET="TRLX_Middle" TITLE="Download Installation"><U><B>HDLMAKER.SH</B></U></A></div> </td> <td valign="top" height=390 BGCOLOR="#FFFFFF" TEXT="#080000"> <div> <B>HDLmaker is offered free of charge by Polybus Systems corporation under a BSD style open source </B><A HREF="id27.htm" TARGET="_top" TITLE="License"><U><B>license</B></U></A><B>. </B></div> <div> Polybus offers Intellectual Property and FPGA and ASIC design services. For information on Polybus' InfiniBand cores for ASICs and FPGAs see,</div> <bR> <div> <A HREF="http://www.polybus.com/ib_link_layer_website/" TARGET="_top" TITLE="http://www.polybus.com/ib_link_layer_web"><U>http://www.polybus.com/ib_link_layer_website/</U></A></div> <bR> <div> If you are interested in licensing our InfiniBand IP or need FPGA or ASIC design consulting please contact Joshua Rosen <A HREF="mailto:bjrosen@polybus.com" TARGET="_top" TITLE="mailto:bjrosen@polybus.com"><U>bjrosen@polybus.com</U></A>.</div> <bR> <div> <B> <A NAME="download_software"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>Download HDLmaker (Includes all libraries, Linux binaries)</B></div> <bR> <div>     <A HREF="http://www.polybus.com/hdlmaker_install.tar" TARGET="_top" TITLE="http://www.polybus.com/hdlmaker_install."><U> </U></A><A HREF="http://www.polybus.com/hdlmaker_install.tar" TARGET="_top" TITLE="http://www.polybus.com/hdlmaker_install."><U>HDLmaker</U></A><A HREF="http://www.polybus.com/hdlmaker_install.tar" TARGET="_top" TITLE="http://www.polybus.com/hdlmaker_install."><U> Version</U></A><A HREF="http://www.polybus.com/hdlmaker_install.tar" TARGET="_top" TITLE="http://www.polybus.com/hdlmaker_install."><U> 9.3.7(Sept 18,2010)</U></A></div> <bR> <bR> <div> <B> <A NAME="installing_software"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>Installing HDLmaker</B></div> <div> Untar it, then run the install script which will compile HDLmaker for your architecture.</div> <bR> <div> tar -xvf hdlmaker_install.tar </div> <div> cd hdlmaker_install </div> <div> ./install.csh</div> <bR> <div> <B> <A NAME="installing_the_man_page"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>Installing the Man Page</B></div> <div> Man pages must be installed as root. </div> <bR> <div> cd $HDLMAKER_LIB/sources/hdlmaker_sources</div> <div> su</div> <div> make man</div> <bR> <div> <B> <A NAME="making_and_installing_hdlmaker"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>Making and installing HDLmaker</B></div> <div> The source code for HDLmaker is in the sources/hdlmaker_sources directory.  The code can be built witht he make install command (the install script takes care of this step).</div> <bR> <div> cd $HDLMAKER_LIB/sources/hdlmaker_sources</div> <div> make install</div> <bR> <div> <B> <A NAME="setting_up_paths"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>Setting up paths</B></div> <div> Two scripts are provided to help set up the env variables and paths, one script is for csh/tcsh and the other is for bash shells. The scripts are hdlmaker.cshrc and hdlmaker.sh. The scripts should be sourced in your .cshrc or .bashrc files after you have set the basic HDLmaker environment variables.</div> <bR> <div> <B> <A NAME="setting_up__cshrc_files"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>Setting up .cshrc files</B></div> <div> Add the following to your .cshrc</div> <bR> <div> setenv HDLMAKER_LIB /usr/local/hdlmaker_lib</div> <bR> <div> setenv HDLMAKER_SYNTHESIS xst</div> <div> setenv HDLMAKER_LANGUAGE verilog</div> <div> setenv FPGA_FAMILY spartan3</div> <div> setenv HDLMAKER_COMPANY "Polybus Systems, Westford MA"</div> <div> setenv HDLMAKER_ENGINEER "B. Joshua Rosen"</div> <bR> <div> source $HDLMAKER_LIB/csh/hdlmaker.cshrc</div> <bR> <div> <B> <A NAME="setting_up__bashrc_files"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>Setting up .bashrc files</B></div> <div> Add the following to your .cshrc</div> <bR> <div> export HDLMAKER_LIB=/usr/local/hdlmaker_lib</div> <bR> <div> export HDLMAKER_SYNTHESIS=xst</div> <div> export HDLMAKER_LANGUAGE=verilog</div> <div> export FPGA_FAMILY=spartan3</div> <div> export HDLMAKER_COMPANY="Polybus Systems, Westford MA"</div> <div> export HDLMAKER_ENGINEER="B. Joshua Rosen"</div> <bR> <div> source $HDLMAKER_LIB/csh/hdlmaker.sh</div> <bR> <div> <B> <A NAME="environment_variables"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>Required </B><B>Environment Variables</B></div> <div> <B> <A NAME="hdlmaker_lib"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>HDLMAKER_LIB</B></div> <div> HDLMAKER<FONT SIZE="3" COLOR="#000000" FACE="Arial" >_LIB specifies the path to the HDLmaker installation. Example:</FONT></div> <bR> <div> setenv HDLMAKER_LIB {/usr/tools/hdlmaker_lib}</div> <bR> <bR> <div> <B> <A NAME="optional_environment_variables"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>Optional Environment Variables</B></div> <div> HDLmaker environment variables may be defined as standard UNIX environment variable,  or in the polybus.lib file or in an HDLmaker .top file. Some variables may also be specified on the command line.</div> <div> If the variable is defined in multiple places then the precedence order is as follows</div> <bR> <div> 1)Command line</div> <div> 2).top File</div> <div> 3)polybus.lib</div> <div> 4)UNIX environment variable</div> <bR> <div> <B> <A NAME="hdlmaker_language"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>HDLMAKER_LANGUAGE</B></div> <div> HDLMAKER_LANGUAGE <FONT SIZE="3" COLOR="#000000" FACE="Bookman Old Style" >specifies </FONT>the default language of the HDLmaker output. The legal options are verilog and vhdl. Examples:</div> <bR> <div> setenv HDLMAKER_LANGUAGE verilog</div> <bR> <div> The default language may be overridden at the command line level with the switches -verilog and -vhdl, example:</div> <bR> <div> hdlmaker -verilog foo.top</div> <bR> <div> or</div> <bR> <div> hdlmaker -vhdl foo.top</div> <bR> <div> <B> <A NAME="hdlmaker_company"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>HDLMAKER_COMPANY</B></div> <div> HDLMAKER_COMPANY specifies the copyright holder of the design. HDLmaker inserts a standard copyright notice at the top of the generated Verilog and VHDL files. The HDLMAKER_COMPANY env variable can be overridden by the #company statement in a .top file, by the HDLMAKER_COPYRIGHT env variable or a #copyright statement in the .top file. The following are equivalent:</div> <bR> <div> setenv HDLMAKER_COMPANY "Polybus Systems Corp., Westford, MA"</div> <bR> <div> In the .top file</div> <div> #company "Polybus Systems Corp., Westford, MA";  // A .top file statement</div> <bR> <div> In polybus.lib</div> <div> #HDLMAKER_LIB "Polybus Systems Corp., Westford, MA";</div> <bR> <div> On the command line</div> <div> hdlmaker -company "Polybus Systems Corp., Westford, MA" foo.top</div> <bR> <div> Both will generate the following copyright statement:</div> <bR> <div> //-- Copyright (c) 2001 Polybus Systems Corp., Westford, MA</div> <div> //-- The information contained in this file is confidential and proprietary.   </div> <div> //-- Any reproduction, use or disclosure, in whole or in part, of this         </div> <div> //-- program, including any attempt to obtain a human-readable version of this </div> <div> //-- program, without the express, prior written consent of Polybus Systems Corp., Westford, MA             </div> <div> //-- is strictly prohibited. </div> <bR> <div> <B> <A NAME="hdlmaker_engineer"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>HDLMAKER_ENGINEER</B></div> <div> HDLMAKER_ENGINEER specifies the name of the designer. A #engineer statement in the .top file overrides the HDLMAKER_ENGINEER env variable. The following are equivalent:</div> <bR> <div> setenv HDLMAKER_ENGINEER "B. Joshua Rosen"</div> <bR> <div> In the .top file</div> <div> #engineer "B. Joshua Rosen";</div> <bR> <div> In polybus.lib</div> <div> #HDLMAKER_ENGINEER "B. Joshua Rosen";</div> <bR> <div> Both will generate the following copyright statement:</div> <bR> <div> //-- Engineer: B. Joshua Rosen</div> <bR> <div> <B> <A NAME="hdlmaker_copyright"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>HDLMAKER_COPYRIGHT</B></div> <div> HDLMAKER_COPYRIGHT specifies a path name to a master copyright statement file. A #copyright statement in the .top file takes precedence over the HDLMAKER_COPYRIGHT env variable. Both take precedence over the HDLMAKER_COMPANY env variable and #company .top statement. The following are equivalent:</div> <bR> <div> setenv HDLMAKER_COPYRIGHT $HDLMAKER_LIB/copyright_files/polybus.bsd</div> <bR> <div> In the .top file</div> <div> #copyright "$HDLMAKER_LIB/copyright_files/polybus.bsd";</div> <bR> <div> In polybus.lib</div> <div> #HDLMAKER_COPYRIGHT "$HDLMAKER_LIB/copyright_files/polybus.bsd";</div> <bR> <div> In this example the following would be generated:</div> <bR> <div> //-- Copyright (c) 2001 Polybus Systems Corp. All rights reserved.</div> <div> //-- </div> <div> //-- Redistribution and use in source and binary forms, with or without</div> <div> //-- modification, are permitted provided that the following conditions</div> <div> //-- are met:</div> <div> //-- </div> <div> //-- 1. Redistributions of source code must retain the above copyright</div> <div> //-- notice, this list of conditions and the following disclaimer.</div> <div> //-- </div> <div> //-- 2. Redistributions in binary form must reproduce the above copyright</div> <div> //-- notice, this list of conditions and the following disclaimer in the</div> <div> //-- documentation and/or other materials provided with the distribution.</div> <div> //-- </div> <div> //-- 3. All advertising materials mentioning features or use of this software</div> <div> //-- must display the following acknowledgment:</div> <div> //-- This product includes software developed by the Polybus Systems Corporation.</div> <div> //-- </div> <div> //-- 4. Neither the name of Polybus System Corporation or the names of its contributors</div> <div> //-- may be used to endorse or promote products derived from this software</div> <div> //-- without specific prior written permission.</div> <div> //-- </div> <div> //-- THIS SOFTWARE IS PROVIDED BY POLYBUS SYSTEMS CORP. AND IT'S CONTRIBUTORS "AS IS" AND</div> <div> //-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE</div> <div> //-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE</div> <div> //-- ARE DISCLAIMED. IN NO EVENT SHALL THE POLYBUS SYSTEMS CORP. OR CONTRIBUTORS BE LIABLE</div> <div> //-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL</div> <div> //-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS</div> <div> //-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)</div> <div> //-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT</div> <div> //-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY</div> <div> //-- OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF</div> <div> //-- SUCH DAMAGE.</div> <bR> <div> <B> <A NAME="hdlmaker_case_sens"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>HDLMAKER_CASE_SENS</B></div> <div> HDLMAKER_CASE_SENS enables case sensitivity. For Verilog designs this variable should be set to TRUE, for VHDL it should be set to FALSE. The .top file directive #casesensitive takes precedence over the HDLMAKER_CASE_SENS env variable.</div> <bR> <div> setenv HDLMAKER_CASE_SENS TRUE</div> <bR> <div> In the .top file</div> <div> #casesensitive; // This enables case sensitivity, the default is not case sensitive</div> <bR> <div> In polybus.lib</div> <bR> <div> #HDLMAKER_CASE_SENS "1";</div> <bR> <div> <B> <A NAME="hdlmaker_synthesis"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>HDLMAKER_SYNTHESIS</B></div> <div> The HDLMAKER_SYNTHESIS env variable specifies the target synthesis tool. Hdlmaker generates tool specific scripts and Make files. It also inserts tool specific directives into the hdl code. The supported tools are:</div> <bR> <div> <IMG BORDER="0" SRC="Symb075c002d00f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">synplicity, (Synplify)</div> <div> <IMG BORDER="0" SRC="Symb075c002d00f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">synopsys, (design compiler and fpga_compiler)</div> <div> <IMG BORDER="0" SRC="Symb075c002d00f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">xst</div> <div> <IMG BORDER="0" SRC="Symb075c002d00f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">quartus</div> <bR> <div> Synplicity and Synopsis have the best support, exemplar's support is probably out of date. There is no support for fpga_express.</div> <bR> <div> To specify Synplify as the synthesis target:</div> <bR> <div> setenv HDLMAKER_SYNTHESIS synplicity</div> <bR> <div> In polybus.lib</div> <bR> <div> #HDLMAKER_SYNTHESIS "synplicity";</div> <bR> <div> <B> <A NAME="hdlmaker_simulator"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>HDLMAKER_SIMULATOR</B></div> <div> The HDLMAKER_SIMULATOR env variable specifies the target simulation tool. HDLmaker creates tool specific scripts for most popular simulation tools. The legal values for the HDLMAKER_SIMULATOR variable are:</div> <bR> <div> <IMG BORDER="0" SRC="Symb075c002d00f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">finsim (Fintronics Finsim)</div> <div> <IMG BORDER="0" SRC="Symb075c002d00f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">verilogxl (Cadence VerilogXL)</div> <div> <IMG BORDER="0" SRC="Symb075c002d00f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">vcs (Synopsys VCS)</div> <div> <IMG BORDER="0" SRC="Symb075c002d00f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">leapfrog (Cadence Leapfrog)</div> <div> <IMG BORDER="0" SRC="Symb075c002d00f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">ncverilog (Cadence ncverilog)</div> <div> <IMG BORDER="0" SRC="Symb075c002d00f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">nc_sim (Cadence NC-Sim)</div> <div> <IMG BORDER="0" SRC="Symb075c002d00f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">modeltech</div> <bR> <div> setenv HDLMAKER_SIMULATOR ncverilog</div> <bR> <bR> <div> <B> <A NAME="hdlmaker_verilog_cmd"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>HDLMAKER_VERILOG_CMD</B></div> <div> HDLmaker generate an ordered list of source files called design_name_v.cmd (where design_name.top is the top level .top file and design_name.v is the top level verilog file). The HDLMAKER_VERILOG_CMD specifies a string that is inserted in the head of the _v.cmd file. For example consider a testbench where the top level file is called sys.top. If you specify an empty string</div> <bR> <div> setenv HDLMAKER_VERILOG_CMD ""</div> <bR> <div> then you could invoke verilogxl as follows</div> <bR> <div> verilog -f sys_v.cmd</div> <bR> <div> You could also put the verilog command in the sys_v.cmd file,</div> <bR> <div> setenv HDLMAKER_VERILOG_CMD "verilog"</div> <bR> <div> then you could invoke verilogxl as follows</div> <bR> <div> ./sys_v.cmd</div> <bR> <div> <B> <A NAME="hdlmaker_family"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>HDLMAKER_FAMILY</B></div> <div> HDLmaker has a set of libraries which contain family specific information about various FPGA families. These libraries contain IO component information, package pinouts, simulation models, synthesis commands and component designs. The libraries are located under the hdlmaker_lib directory.</div> <bR> <div> The supported families are:</div> <bR> <div> <IMG BORDER="0" SRC="Symb075c002d00f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">xc4000</div> <div> <IMG BORDER="0" SRC="Symb075c002d00f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">xc4000e</div> <div> <IMG BORDER="0" SRC="Symb075c002d00f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">xc4000ex</div> <div> <IMG BORDER="0" SRC="Symb075c002d00f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">xc4000xl</div> <div> <IMG BORDER="0" SRC="Symb075c002d00f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">xc9500</div> <div> <IMG BORDER="0" SRC="Symb075c002d00f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">xc9500-xl</div> <div> <IMG BORDER="0" SRC="Symb075c002d00f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">Virtex</div> <div> <IMG BORDER="0" SRC="Symb075c002d00f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">Virtexe</div> <div> <IMG BORDER="0" SRC="Symb075c002d00f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">Virtex2</div> <div> <IMG BORDER="0" SRC="Symb075c002d00f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">Virtex2p</div> <div> <IMG BORDER="0" SRC="Symb075c002d00f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">Virtex2px</div> <div> <IMG BORDER="0" SRC="Symb075c002d00f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">Virtex4</div> <div> <IMG BORDER="0" SRC="Symb075c002d00f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">Virtex5</div> <div> <IMG BORDER="0" SRC="Symb075c002d00f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">Virtex6</div> <div> <IMG BORDER="0" SRC="Symb075c002d00f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">orca2c</div> <div> <IMG BORDER="0" SRC="Symb075c002d00f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">orca2ca</div> <div> <IMG BORDER="0" SRC="Symb075c002d00f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">spartan</div> <div> <IMG BORDER="0" SRC="Symb075c002d00f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">spartan-xl</div> <div> <IMG BORDER="0" SRC="Symb075c002d00f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">spartan2</div> <div> <IMG BORDER="0" SRC="Symb075c002d00f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">spartan2e</div> <div> <IMG BORDER="0" SRC="Symb075c002d00f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">spartan3</div> <div> <IMG BORDER="0" SRC="Symb075c002d00f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">spartan3e</div> <div> <IMG BORDER="0" SRC="Symb075c002d00f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">xc5200</div> <div> <IMG BORDER="0" SRC="Symb075c002d00f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">Stratix</div> <div> <IMG BORDER="0" SRC="Symb075c002d00f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">Stratixiigx</div> <div> <IMG BORDER="0" SRC="Symb075c002d00f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">Stratixivgx (includes gt as well as gx)</div> <div> <IMG BORDER="0" SRC="Symb075c002d00f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">AcronixSpeedster</div> <bR> <div> setenv HDLMAKER_FAMILY virtexe</div> <bR> <div> In the .top file</div> <div> #family "spartan2";</div> <bR> <div> In polybus.lib</div> <bR> <div> #family "spartan2";</div> <bR> <div> <B> <A NAME="hdlmaker_map_effort"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>HDLMAKER_MAP_EFFORT</B></div> <div> This is a Synopsys design compiler specific variable. If defined this variable will put the specified map_effort directive into the Synopsys design compiler scripts (.job file).</div> <bR> <div> setenv HDLMAKER_SYNOPSYS_MAP_EFFORT "high"</div> <bR> <div> <B> <A NAME="hdlmaker_upcase_io"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>HDLMAKER_UPCASE_IO</B></div> <div> Hdlmaker uses different IO component models for simulation and synthesis. For simulation a lower case component name is used, for synthesis an upper case name is used (i.e. fd.v versus FD.v). This is a legacy of the Xilinx XC4000 family which had a hidden reset line in the IO flops. The HDLMAKER_UPCASE_IO env variable tells HDLmaker to upcase IO component names when producing synthesis code.  For Xilinx FPGAs you should set this variable to 1.</div> <bR> <div> setenv HDLMAKER_UPCASE_IO 1</div> <bR> <div> <B> <A NAME="schematic_layout"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>Schematic Layout Environment Variables</B></div> <div> HDLmaker can generate schematics for designs of type "board". The WIDTH and HEIGHT variables specify the page dimensions in tenths of an inch. The ROTATE variable specifies landscape (1) or portrait (0) layout, The PLACE_VERTICALLY variable specifies the direction in which the components are placed on the page. PLACE_VERTICALLY 1 will start at the top left hand corner and place from top to bottom. PLACE_VERTICALLY 0 places the components from left to right. The schematic generator places components in the order that they are found in the .top file.</div> <bR> <div> setenv HDLMAKER_PAGE_WIDTH 100</div> <div> setenv HDLMAKER_PAGE_HEIGHT 75</div> <div> setenv HDLMAKER_PAGE_ROTATE 1</div> <div> setenv HDLMAKER_PLACE_VERTICALLY 1</div> <bR> <div> <B> <A NAME="hdlmaker_set_defparam"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B></div> <div> <B>HDLMAKER_SET_DEFPARAM</B></div> <div> Verilog has two methods of passing parameters, by argument and with the defparam statement. HDLmaker supports both methods. To use defparam set the SET_DEFPARAM variable to 1, to use the argument method set it to 0. Generally the defparam method is better because it doesn't require you to specify all of the parameters, only those parameters which differ from the default.</div> <bR> <div> setenv HDLMAKER_SET_DEFPARAM 1</div> <bR> <div> <B> <A NAME="hdlmaker_local_copy"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>HDLMAKER_LOCAL_COPY</B></div> <div> Copy all files to the local directories. When set to TRUE HDLmaker will copy all files to the appropriate local directory (.v to ../v, .vhd to ../vhd, .top to ../top and so forth). In addition all files generated by HDLMaker will be saved in the appropriate local directory. When set to FALSE HDLmaker does not make local copies. HDLmaker generated files will be saved in the subdirectories associated with each .top file in the design. For example if HDLmaker finds a top file called foo.top in the directory ../bar/top/foo.top then it will place the resulting .v file (say foo.v) into the related v directory, ../bar/v/foo.v. The one exception to the rule are script files that are stored in both the related script directory (in this example ../bar/scripts) and into the local script directory (../script). Large projects which consist of multiple sub-projects should set the LOCAL_COPY directory to FALSE, small projects may find it convenient to set LOCAL_COPY to TRUE. Earlier versions of HDLmaker always made local copies so setting this variable to TRUE will mimic the behavior the earlier versions.</div> <bR> <div> setenv HDLMAKER_LOCAL_COPY FALSE</div> <bR> <div> In the polybus.lib</div> <bR> <div> #HDLMAKER_LOCAL_COPY TRUE</div> <bR> <div> <B> <A NAME="hdlmaker_use_sub_dir"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>HDLMAKER_USE_SUB_DIR</B></div> <div> Modify relative pathnames inside of scripts to account for the use of a subdirectory. For must applications you will want to set this variable to TRUE or 1. The example below illustrates to effect of this variable. For a the module ../bar/v/foo.v the path used in a script would be</div> <bR> <div> setenv HDLMAKER_USE_SUB_DIRECTORY FALSE</div> <bR> <div> ../bar/v/foo.v</div> <bR> <div> setenv HDLMAKER_USE_SUB_DIRECTORY TRUE</div> <bR> <div> ../../v/foo.v</div> <bR> <div> a local file, v/foobar.v, would be referenced as </div> <bR> <div> setenv HDLMAKER_USE_SUB_DIRECTORY FALSE</div> <bR> <div> v/foo.v</div> <bR> <div> setenv HDLMAKER_USE_SUB_DIRECTORY TRUE</div> <bR> <div> ../v/foo.v</div> <bR> <div> In polybus.lib</div> <bR> <div> #HDLMAKER_USE_SUB_DIRECTORY FALSE</div> <div> <B> <A NAME="hdlmaker_gen_date"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>HDLMAKER_GEN_DATE</B></div> <div> Include the generation date in the header. Default is FALSE.</div> <bR> <div> <B> <A NAME="hdlmaker_allow_sub"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>HDLMAKER_ALLOW_SUB</B></div> <div> Allow the substitution of an existing Verilog or VHDL file if a .top file is not found.  The default is FALSE.</div> <bR> <div> #HDLMAKER_UALLOW_SUB TRUE</div> <bR> <div> <B> <A NAME="hdlmaker_cshrc"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>HDLMAKER.CSHRC</B></div> <div> A csh script is provided in <A HREF="http://www.polybus.com/hdlmaker/hdlmaker.cshrc.html" TARGET="_top" TITLE="http://www.polybus.com/hdlmaker/hdlmaker"><U>$HDLMAKER_LIB/csh/hdlmaker.cshrc</U></A> which you may source in your .cshrc file to set the required HDLmaker env variables.</div> <bR> <div> source $HDLMAKER_LIB/csh/hdlmaker.cshrc</div> <bR> <div> <B> <A NAME="hdlmaker_sh"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>HDLMAKER.SH</B></div> <div> A bashscript is provided in <A HREF="http://www.polybus.com/hdlmaker/hdlmaker.cshrc.html" TARGET="_top" TITLE="http://www.polybus.com/hdlmaker/hdlmaker"><U>$HDLMAKER_LIB/csh/hdlmaker.</U></A>sh which you may source in your .bashrc file to set the required HDLmaker env variables.</div> <bR> <div> source $HDLMAKER_LIB/csh/hdlmaker.sh</div> <bR> <bR> <bR> </td> </tr></table></body>