HDLMAKER(1) User Commands HDLMAKER(1)
NAME
hdlmaker - manual page for hdlmaker
DESCRIPTION
/usr/local/tools/hdlmaker_lib/doc/vhdl_overview.help
hdlmaker generates vhdl and verilog code,scripts and Makefiles for both
simulation and synthesis.
hdlmaker [-simulate][-xst][-quartus][-modeltech] filename.xxx
File extensions:
.cvrt Convert a list of text files to the specified format
(default UNIX).
.flist File list (for NC and VCS).
.miflist List of Quartus generated MIF files to be converted
into Verilog ROM files.
.net Hdlmaker netlist format. Produced automatically when
the -cnet,-pnet,-schematic,or -pads switches are applied to a .top file
i.e. hdlmaker -pads foo.top.
.pin A pin list used to generate a Xilinx pad ring.
.prj Synplify project file.
.qsf Altera Quartus project file.
.sdc Synopsis constraint file.
.template Component connection template.
.top A top level file which connects a series of components.
.ucf Xilinx user constraint file.
.v Verilog file.
.vhd VHDL file.
.xprj XST project file.
.xscr XST script file.
Switches:
-autopin Automatically pins the part. Pins are assigned to
sequential pads. Only unassigned pins are effected.
-board Include the non-IO pins on the entity or module gener-
ated from a .pin file. I.E. include grounds,power,jtag, initialization
..., Use the -board switch when building’pc boards, don’t use it when
building an FPGA. A #part_type "board" has the same effect.
-casesensitive Do not downcase code (Use for verilog only). Allow the
use of uppercase characters in file names and Verilog module and signal
names.
-cnettotop Generate a .top file from a .cnet or .alg file.
-copy Copy all files to the local directory
-coverage Set up the Makefiles and scripts to run code coverage
-dos All generated files are in DOS format
-edif Force Synopsys to write out a SEDIF file. The defaults
are SXNF format for Xilinx and SEDIF of Lucent
-family xxx Overrides the family in the top file
-html Generate hyperlinked, syntax colored HTML files. Works
on any kind of source file.
-library xxx Specifies the selected directory as the primary library
-make_args Set up the Modelsim Makefiles to take an argument for
compile switchs. Example S="+define+fpga" -f make/foo.make
-makeinclude Convert a .net file into a c include file
-makepinfile Generate a .pin file for every vhdl or verilog compo-
nent that doesn’t have one.
-makepinfromnet Extract the pin files from a .cnet netlist. These pin
files can be used to create models of the components in a netlist or as
back annotation files, hdlmaker -makepinfromnet foo.cnet.
-map_effort Overrides the HDLMAKER_SYNOPSYS_MAP_EFFORT env vari-
able, sets the Synopsys map_effort level
-modeltech Overrides the HDLMAKER_SIMULATOR env variable to force
hdlmaker to generate Modelsim and Quartus Makefiles and scripts.
-noreset Never add an async reset. If neither gblreset or nore-
set is set then hdlmaker adds gblreset to all registers in any abel
file that doesn’t have a device field
-package xxx Overrides the package in the top file
-part_type xxx Overrides the parttype in the top file
-partition Generate a partition report (.cnct) which can be used
to partition design into two packages. The partition report orders the
components via two different algorithms, one which seeks to reduce the
number of interconnects between the two groups, and one which maximizes
the connectivity within each group. In addition, when used in conjuc-
tion with the Synopsys FPGA compiler,in lists the percentage of the
total number of CLBs used at each partion cut.
-placevertical Place the components on the schematic page from top to
bottom instead of from left to right
-quartus Overrides the HDLMAKER_SYNTHESYS env variable to force
the generation of Altera Quartus projects
-repin Completely re-pins the part.
-reverse Reverse the order in which autopin and repin assign
pins. Default orders is foo[7:0] will be assigned from 7 to 0. Reverse
assigns from 0 to 7
-rotate Schematic orientation, 0 = portrait, 1 = landscape HDL-
MAKER_PAGE_ROTATE env variable defines the default
-schematic Make a TCL schematic. Run a TCL app like WISH to view
the schematics and to produce postscript versions.
-simulate Generates special code for simulation (default synthe-
sis code)
-speed xxx Overrides the speed in the top file
-src_copy Copy a clean tree (excluding the hdlmaker files) to the
release directory. Copies ".v",".vhd",".h",".vh",".defs" files.
-stimulus Makes an empty stimulus file. The pins on the entity
are a mirror image of the pins in the .pin file (for top files) or the
pins on the connector for a pc board.
-stripp Strip off the leading Ps in pin numbers
-synopsys Overrides the HDLMAKER_SYNTHESYS env variable to force
the generation of Synopsys compatible vhdl files (most importantly the
pad ring file);
-synplicity Overrides the HDLMAKER_SYNTHESYS env variable to force
the generation of Synplicity compatible vhdl files (most importantly
the pad ring file);
-tree_copy Copy a clean tree to the release directory. Copies
".v",".vhd",".h",".vh",".defs",".list",".top",".pin" files.
-unix All generated files are in Unix format (default)
-upcase_io Overrides the HDLMAKER_UPCASE_IO env variable, If 1 the
IO component names will be upcased for synthesys (but not for simula-
tion). Upcase_io is used for Verilog, ignored for VHDL.
-update Update the local copies of the library components
-verilog Overrides the HDLMAKER_LANGUAGE env variable to force
hdlmaker to generate verilog.
-verilogxl Overrides the HDLMAKER_SIMULATOR env variable to force
hdlmaker to generate VerilogXL scripts
-version Print Version.
-vhdl Overrides the HDLMAKER_LANGUAGE env variable to force
hdlmaker to generate VHDL.
-width Page width of the schematic in .1 inch increments, for
example 8.5 inches is 85 HDLMAKER_PAGE_WIDTH env variable defines the
default
-wrap Generate .wrap file,
-xnf Force Synopsys to write out a SXNF file
-xst Overrides the HDLMAKER_SYNTHESYS env variable to force
the generation of Xilinx XST projects
EXAMPLES
hdlmaker -modeltech foo.top
hdlmaker -quartus foo.top
hdlmaker -xst foo.top
hdlmaker -tree_copy foo.top
hdlmaker -mac foo.cvrt
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polybus.lib Search path file
The polybus.lib file contains a search path list for HDLmaker. The
directories are searched in order starting with the local directory,
followed by the directories in polybus.lib, and then the hdlmaker stan-
dard libraries. You can also place environment varibles in the poly-
bus.lib file.
Example polybus.lib file
#family "stratixivgx";
#part_type "EP4S100G2F40";
#speed "I2";
#package "1517";
#HDLMAKER_USE_SUB_DIR "FALSE";
#HDLMAKER_LOCAL_COPY "FALSE";
#HDLMAKER_UNIVERSAL "TRUE";
#HDLMAKER_SYNTHESIS "QUARTUS";
#define "me" "../s4gt";
#define "crc" "../../../cores/aqdr_link_layer/crc";
#define "a_pcs" "../../../cores/aqdr_link_layer/pcs";
hdlmaker (c) 1994 - 2010 Polybus Systems Corp, Rev 9.3.7 (09/16/2010)
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