Running HDLmaker

<body topmargin=0 leftmargin=0 marginheight=0 marginwidth=0> <table cellpadding=0 cellspacing=0 border=0><tr> <td valign="top" colspan=2 height=90 BGCOLOR="#CC9900" TEXT="#080000" bgproperties="fixed" background="045005a0dwnjzk.gif"> <div> <A HREF="index.htm" TARGET="_top" TITLE="HDLmaker"><U><B>home</B></U></A><B>     | </B><B> </B><B> </B><B>  </B><FONT SIZE="5" COLOR="#FFCC66" FACE="Arial" ><B>HDLmaker</B></FONT></div> <div> <A HREF="id17.htm" TARGET="_top" TITLE="Download Installation"><U><B>Download & Installation</B></U></A><B>   |   </B><B>Running HDLmaker</B><B>   |   </B><A HREF="id20.htm" TARGET="_top" TITLE="Users Manual"><U><B>Users Manual</B></U></A><B>   |   </B><A HREF="id27.htm" TARGET="_top" TITLE="License"><U><B>License</B></U></A><B>   |   </B><A HREF="id19.htm" TARGET="_top" TITLE="Contact Us"><U><B>Contact Us</B></U></A><B>   |   </B><A HREF="id31.htm" TARGET="_top" TITLE="Help"><U><B>Help</B></U></A></div> <div> </div> </td> </tr><tr> <td valign="top" width=210 BGCOLOR="#FFFFFF" TEXT="#080000"> <div> Running HDLmaker</div> <div> <B><IMG SRC="05e69830.gif" border=0 width="105" height="131" ALIGN="BOTTOM" HSPACE="0" VSPACE="0"></B><A HREF="http://www.polybus.com" TARGET="_top" TITLE="http://www.polybus.com"><U><B>Polybus</B></U></A></div> </td> <td valign="top" height=390 BGCOLOR="#FFFFFF" TEXT="#080000"> <div> HDLMAKER(1)                      User Commands                     HDLMAKER(1)</div> <bR> <bR> <bR> <div> NAME</div> <div>        hdlmaker - manual page for hdlmaker</div> <bR> <div> DESCRIPTION</div> <div>        /usr/local/tools/hdlmaker_lib/doc/vhdl_overview.help</div> <bR> <div>        hdlmaker generates vhdl and verilog code,scripts and Makefiles for both</div> <div>        simulation and synthesis.</div> <bR> <div>        hdlmaker [-simulate][-xst][-quartus][-modeltech] filename.xxx</div> <bR> <div>        File extensions:</div> <bR> <div>        .cvrt           Convert a list of text files to  the  specified  format</div> <div>        (default UNIX).</div> <bR> <div>        .flist          File list (for NC and VCS).</div> <bR> <div>        .miflist         List  of  Quartus  generated MIF files to be converted</div> <div>        into Verilog ROM files.</div> <bR> <div>        .net            Hdlmaker netlist format.  Produced  automatically  when</div> <div>        the -cnet,-pnet,-schematic,or -pads switches are applied to a .top file</div> <div>        i.e. hdlmaker -pads foo.top.</div> <bR> <div>        .pin            A pin list used to generate a Xilinx pad ring.</div> <bR> <div>        .prj            Synplify project file.</div> <bR> <div>        .qsf            Altera Quartus project file.</div> <bR> <div>        .sdc            Synopsis constraint file.</div> <bR> <div>        .template       Component connection template.</div> <bR> <div>        .top            A top level file which connects a series of components.</div> <bR> <div>        .ucf            Xilinx user constraint file.</div> <bR> <div>        .v              Verilog file.</div> <bR> <div>        .vhd            VHDL file.</div> <bR> <div>        .xprj           XST project file.</div> <bR> <div>        .xscr           XST script file.</div> <bR> <div>        Switches:</div> <bR> <div>        -autopin         Automatically  pins  the  part.  Pins  are assigned to</div> <div>        sequential pads. Only unassigned pins are effected.</div> <bR> <div>        -board          Include the non-IO pins on the entity or module  gener-</div> <div>        ated  from a .pin file. I.E. include grounds,power,jtag, initialization</div> <div>        ..., Use the -board switch when building’pc boards, don’t use  it  when</div> <div>        building an FPGA. A #part_type "board" has the same effect.</div> <bR> <div>        -casesensitive   Do not downcase code (Use for verilog only). Allow the</div> <div>        use of uppercase characters in file names and Verilog module and signal</div> <div>        names.</div> <bR> <div>        -cnettotop      Generate a .top file from a .cnet or .alg file.</div> <bR> <div>        -copy           Copy all files to the local directory</div> <bR> <div>        -coverage       Set up the Makefiles and scripts to run code coverage</div> <bR> <div>        -dos            All generated files are in DOS format</div> <bR> <div>        -edif            Force Synopsys to write out a SEDIF file. The defaults</div> <div>        are SXNF format for Xilinx and SEDIF of Lucent</div> <bR> <div>        -family    xxx  Overrides the family in the top file</div> <bR> <div>        -html           Generate hyperlinked, syntax colored HTML files.  Works</div> <div>        on any kind of source file.</div> <bR> <div>        -library   xxx  Specifies the selected directory as the primary library</div> <bR> <div>        -make_args      Set up the Modelsim Makefiles to take an  argument  for</div> <div>        compile switchs. Example S="+define+fpga" -f make/foo.make</div> <bR> <div>        -makeinclude    Convert a .net file into a c include file</div> <bR> <div>        -makepinfile     Generate  a .pin file for every vhdl or verilog compo-</div> <div>        nent that doesn’t have one.</div> <bR> <div>        -makepinfromnet Extract the pin files from a .cnet netlist.  These  pin</div> <div>        files can be used to create models of the components in a netlist or as</div> <div>        back annotation files, hdlmaker -makepinfromnet foo.cnet.</div> <bR> <div>        -map_effort     Overrides the  HDLMAKER_SYNOPSYS_MAP_EFFORT  env  vari-</div> <div>        able, sets the Synopsys map_effort level</div> <bR> <div>        -modeltech       Overrides the HDLMAKER_SIMULATOR env variable to force</div> <div>        hdlmaker to generate Modelsim and Quartus Makefiles and scripts.</div> <bR> <div>        -noreset        Never add an async reset. If neither gblreset or  nore-</div> <div>        set  is  set  then  hdlmaker adds gblreset to all registers in any abel</div> <div>        file that doesn’t have a device field</div> <bR> <div>        -package   xxx  Overrides the package in the top file</div> <bR> <div>        -part_type xxx  Overrides the parttype in the top file</div> <bR> <div>        -partition      Generate a partition report (.cnct) which can  be  used</div> <div>        to  partition design into two packages. The partition report orders the</div> <div>        components via two different algorithms, one which seeks to reduce  the</div> <div>        number of interconnects between the two groups, and one which maximizes</div> <div>        the connectivity within each group. In addition, when used  in  conjuc-</div> <div>        tion  with  the  Synopsys  FPGA compiler,in lists the percentage of the</div> <div>        total number of CLBs used at each partion cut.</div> <bR> <div>        -placevertical  Place the components on the schematic page from top  to</div> <div>        bottom instead of from left to right</div> <bR> <div>        -quartus         Overrides the HDLMAKER_SYNTHESYS env variable to force</div> <div>        the generation of Altera Quartus projects</div> <bR> <div>        -repin          Completely re-pins the part.</div> <bR> <div>        -reverse        Reverse the order in which  autopin  and  repin  assign</div> <div>        pins.  Default orders is foo[7:0] will be assigned from 7 to 0. Reverse</div> <div>        assigns from 0 to 7</div> <bR> <div>        -rotate         Schematic orientation, 0 = portrait, 1 = landscape HDL-</div> <div>        MAKER_PAGE_ROTATE env variable defines the default</div> <bR> <div>        -schematic       Make  a TCL schematic. Run a TCL app like WISH to view</div> <div>        the schematics and to  produce postscript versions.</div> <bR> <div>        -simulate       Generates special code for simulation (default  synthe-</div> <div>        sis code)</div> <bR> <div>        -speed     xxx  Overrides the speed in the top file</div> <bR> <div>        -src_copy       Copy a clean tree (excluding the hdlmaker files) to the</div> <div>        release directory. Copies ".v",".vhd",".h",".vh",".defs" files.</div> <bR> <div>        -stimulus       Makes an empty stimulus file. The pins  on  the  entity</div> <div>        are  a mirror image of the pins in the .pin file (for top files) or the</div> <div>        pins on the connector for a pc board.</div> <bR> <div>        -stripp         Strip off the leading Ps in pin numbers</div> <bR> <div>        -synopsys       Overrides the HDLMAKER_SYNTHESYS env variable to  force</div> <div>        the  generation of Synopsys compatible vhdl files (most importantly the</div> <div>        pad ring file);</div> <bR> <div>        -synplicity     Overrides the HDLMAKER_SYNTHESYS env variable to  force</div> <div>        the  generation  of  Synplicity compatible vhdl files (most importantly</div> <div>        the pad ring file);</div> <bR> <div>        -tree_copy      Copy a clean tree  to  the  release  directory.  Copies</div> <div>        ".v",".vhd",".h",".vh",".defs",".list",".top",".pin" files.</div> <bR> <div>        -unix           All generated files are in Unix format (default)</div> <bR> <div>        -upcase_io      Overrides the HDLMAKER_UPCASE_IO env variable, If 1 the</div> <div>        IO component names will be upcased for synthesys (but not  for  simula-</div> <div>        tion). Upcase_io is used for Verilog, ignored for VHDL.</div> <bR> <div>        -update         Update the local copies of the library components</div> <bR> <div>        -verilog         Overrides  the HDLMAKER_LANGUAGE env variable to force</div> <div>        hdlmaker to generate verilog.</div> <bR> <div>        -verilogxl      Overrides the HDLMAKER_SIMULATOR env variable to  force</div> <div>        hdlmaker to generate VerilogXL scripts</div> <bR> <div>        -version        Print Version.</div> <bR> <div>        -vhdl            Overrides  the HDLMAKER_LANGUAGE env variable to force</div> <div>        hdlmaker to generate VHDL.</div> <bR> <div>        -width          Page width of the schematic in .1 inch increments,  for</div> <div>        example  8.5  inches is 85 HDLMAKER_PAGE_WIDTH env variable defines the</div> <div>        default</div> <bR> <div>        -wrap           Generate .wrap file,</div> <bR> <div>        -xnf            Force Synopsys to write out a SXNF file</div> <bR> <div>        -xst            Overrides the HDLMAKER_SYNTHESYS env variable to  force</div> <div>        the generation of Xilinx XST projects</div> <bR> <div> EXAMPLES</div> <div>        hdlmaker -modeltech foo.top</div> <bR> <div>        hdlmaker -quartus foo.top</div> <bR> <div>        hdlmaker -xst foo.top</div> <bR> <div>        hdlmaker -tree_copy foo.top</div> <bR> <div>        hdlmaker -mac foo.cvrt</div> <bR> <div>        ---------------------------------------------------------------------------------</div> <div>        polybus.lib     Search path file</div> <bR> <div>        The polybus.lib file contains a search  path  list  for  HDLmaker.  The</div> <div>        directories  are  searched  in order starting with the local directory,</div> <div>        followed by the directories in polybus.lib, and then the hdlmaker stan-</div> <div>        dard  libraries.  You  can also place environment varibles in the poly-</div> <div>        bus.lib file.</div> <bR> <div>        Example polybus.lib file</div> <bR> <div>        #family "stratixivgx";</div> <bR> <div>        #part_type "EP4S100G2F40";</div> <bR> <div>        #speed "I2";</div> <bR> <div>        #package "1517";</div> <bR> <div>        #HDLMAKER_USE_SUB_DIR   "FALSE";</div> <bR> <div>        #HDLMAKER_LOCAL_COPY    "FALSE";</div> <bR> <div>        #HDLMAKER_UNIVERSAL     "TRUE";</div> <bR> <div>        #HDLMAKER_SYNTHESIS     "QUARTUS";</div> <bR> <div>        #define "me"            "../s4gt";</div> <bR> <div>        #define "crc"           "../../../cores/aqdr_link_layer/crc";</div> <bR> <div>        #define "a_pcs"         "../../../cores/aqdr_link_layer/pcs";</div> <bR> <div>        hdlmaker (c) 1994 - 2010 Polybus Systems Corp, Rev 9.3.7 (09/16/2010)</div> <bR> </td> </tr></table></body>