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sample.pin

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#uselibrary

#pins

tdi               type =rsvd,pin=6;
tclk              type =rsvd,pin=7;
tms               type =rsvd,pin=17;
tdi               type =rsvd,pin=6;
tdo               type =rsvd,pin=181;

init_l                  type =rsvd,pin=89;
prog_l                  type =rsvd,pin=122;
din               type =rsvd,pin=177;
dout              type =rsvd,pin=178;
cclk              type =rsvd,pin=179;
done              type =rsvd,pin=120;

sysclk                  type = clkp,pin = 184;
reset             type = in,pin=124;
mclk[8..9]        type = in,clk=sysclk,pin=[125,186];
probe[1..0]       type = out,clk=sysclk,pin=[187,218];

#endpins






#Summary

      Total Inputs:     4
      Total Outputs:    2
      Total Bidirects:  0
      Total Pins: 6

#endSummary

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HDLMaker Generated Files

sample_pads.v	Verilog file
sample_pads.job	Synopsys script file
sample.pinlist	Pin list sorted by both name and number file
sample.xref	Pin cross reference for PC board models file
sample.prj	Synplicity project file
sample.ucf	Xilinx constraint file file

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