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sample.v

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//-- sample.v
//-- Generated by HDLMAKER Rev 5.6.0, Thursday January 11 2001
//-- Copyright (c) 2001 Polybus Systems Corp, Inc., Westford, MA
//-- The information contained in this file is confidential and proprietary.   
//-- Any reproduction, use or disclosure, in whole or in part, of this         
//-- program, including any attempt to obtain a human-readable version of this 
//-- program, without the express, prior written consent of Polybus Systems Corp, Inc., Westford, MA             
//-- is strictly prohibited.                                       
//-- Engineer: B. Joshua Rosen

module sample(
              mclk_pin,
              probe_pin,
              reset_pin,
              sysclk_pin
              );
   //-- IO Declarations
   input  [9:8] mclk_pin;
   output [1:0] probe_pin;
   input       reset_pin;
   input       sysclk_pin;

   //-- Signal Declarations

   wire [45:0]    a;
   wire [45:0]    b;
   wire [1:0]     clkenb;
   wire           gblreset;
   wire           greset;
   wire [9:8]     mclk;
   wire [1:0]     probe;
   wire           reset;
   wire           sysclk;





   //-- Component Instance sample_pads_1
   sample_pads sample_pads_1
      (

         .gblreset                        (gblreset),
         .mclk_pin                        ({mclk_pin[9:8]}),
         .probe                           ({probe[1:0]}),
         .reset_pin                       (reset_pin),
         .sysclk_pin                      (sysclk_pin),
         .mclk                            ({mclk[9:8]}),
         .probe_pin                       ({probe_pin[1:0]}),
         .reset                           (reset),
         .sysclk                          (sysclk)
      );

   //-- Component Instance startup_1
   STARTUP startup_1
      (

         .GSR                             (greset)
      );

   //-- Component Instance rstbuff_1
   rstbuff rstbuff_1
      (

         .reset                           (reset),
         .greset                          (greset),
         .gblreset                        (gblreset)
      );

   //-- Component Instance accblock_1
   accblock accblock_1
      (

         .clkenb                          (clkenb[0]),
         .gblreset                        (gblreset),
         .sysclk                          (sysclk),
         .a                               ({a[45:0]})
      );

   //-- Component Instance accblock_2
   accblock accblock_2
      (

         .clkenb                          (clkenb[1]),
         .gblreset                        (gblreset),
         .sysclk                          (sysclk),
         .a                               ({b[45:0]})
      );

   //-- Component Instance cmp46_1
   cmp46 cmp46_1
      (

         .cmp_a                           ({a[45:0]}),
         .cmp_b                           ({b[45:0]}),
         .gblreset                        (gblreset),
         .sysclk                          (sysclk),
         .probe                           ({probe[1:0]})
      );

   //-- Component Instance bufgs_1
   bufgs bufgs_1
      (

         .i                               (mclk[8]),
         .o                               (clkenb[0])
      );

   //-- Component Instance bufgs_2
   bufgs bufgs_2
      (

         .i                               (mclk[9]),
         .o                               (clkenb[1])
      );
endmodule

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HDLMaker Generated Files

sample.job

Synopsys script file

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