Polybus offers a family of InfiniBand Link Layer Cores ranging from a Single Data Rate 4X core (10GBit/Second) to a Quad Data Rate 8X core (80GBit/second). All Link Layer cores are available for both Xilinx and Altera FPGAs as well as for ASIC applications.

There are three members of the Link Layer family. The SDR Link Layer Core is the smallest core, it operates at 125 MHz and supports bidirectional speeds of 10GBits/second in each direction. Customers are currently using the SDR core in Xilinx Virtex2P, Xilinx Virtex4FX. Altera Stratix2GX and ASICs. The SDR core can operate in the lowest speed grades of the Virtex4FX (-10) and the Stratix2GX (-5).

The DDR (Double Data Rate) Link Layer Core operates at 250 MHz and supports bidirectional speeds of 20GBits/second. The DDR core requires a 5 GHz SerDes. Customers are using the DDR core in Xilinx Virtex4FX, Altera Stratix2GX and in ASICs. The DDR core requires the middle speed grades of the the Virtex4FX (-11) and the Stratix2GX (-4).

The newest memory of the Polybus core family is the QDR (Quad Data Rate) Link Layer Core. The QDR cores supports 8X operation at DDR speeds (40GBits/Second) in FPGAs at 250 MHz and 8X QDR speeds (80Gbits/Second) at 500 MHz in ASICs.

Polybus offers a family of InfiniBand Transport Layer Cores for use in Data Acquisition, High Performance Computing and Networking Applications.

For Data Acquisition and Networking applications, Polybus offers a 4X Single Data Rate (SDR) Unreliable Connect (UC) Transport Layer Core which supports UC SEND and UC RDMA Write on 1024 simultaneous Queue Pairs. The Core operates at full wire speed when mated with the Polybus SDR Link Layer core. Message sizes of up to 2GBytes are supported.

For High Performance Computing applications, Polybus offers a 4X SDR Reliable Connect (RC) Transport Layer Core. The core handles both reliable and unreliable connections, supports RDMA Read, RDMA Write and SEND operations. The RC Transport Layer also has support for End to End Flow control. The design is optimized for low latency and maximum throughput even on small packet sizes. The buffers can operate in cut-through mode to minimize latency. The core supports 1024 Queue Pairs and 511 Reliable Requests in flight at any one time. Retries are handled completely independently from the client logic. The Advanced Transport Layer Core implements the InfiniBand Architecture Release 1.2 Transport Layer specification.

Both UC and RC TCA configurations are available. The TCAs combine the Transport Layer with a Link Layer to form a highly capable Target Channel Adapter.

A Dual Port Port UC TCA is available which is used to build switchless InfiniBand systems. Multiple Dual Port TCAs can be connected together in either a ring or string topology. The Dual Port TCA supports a multicast mode where data can be sent to multiple targets simultaneously.