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pintest_kernel.top

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#module "pintest_kernel";
#family "virtex";

#include "pintest_kernel.pin";

#int j,k,l,m;

#for(j=0;j<488;j+=2)
{
    #insert "pintest.top",
    connect fb_io[1:0] = fb_data[#j+1:#j],
    connect ram_d = ram_d[#j>>1];
}

#for(j=0;j<6;j+=2)
{
    #assign m = j + 488;
    #insert "pintest.top",
    connect fb_io[1:0] = fb_special[#j+1:#j],
    connect ram_d = ram_d[#m>>1];
}

#for(j=0;j<16;j++)
{
    #assign k = j * 16;
    #assign l = j * 2;
    #insert "RAMB4_S1_S16.v",
    connect DIB[15:0] = ram_d[#k+15:#k],
    connect DOB[15:0] = ram_q[#k+15:#k],
    connect DIA[0:0] = ram_in[#j],
    connect DOA[0:0] = ram_out[#j],
    connect ADDRA[11:0] = scan_addr[11:0],
    connect ADDRB[7:0] = dump_addr[7:0],
    connect CLKA = tclk,
    connect CLKB = sysclk,
    connect WEA = scan_wrt,
    connect WEB = dump_wrt,
    connect RSTA = gblreset,
    connect RSTB = gblreset,
    connect ENA = scan_enb,
    connect ENB = dump_enb;
    
}

#insert "pintest_ctrl.v";

#library_element "RAMB4_S1_S16";

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HDLMaker Generated Files

pintest_kernel.v	Verilog file
pintest_kernel.job	Synopsys script file
pintest_kernel.prj	Synplicity Project file
pintest_kernel.ucf	Xilinx constraint file
pintest_kernel.Make	Synopsy Make file
pintest_kernel_v.cmd	Leapfrog Make file
pintest_kernel_mt.do	Model Tech script file
pintest_kernel_batch.Make	Synopsis batch Make file
pintest_kernel.errors	DRC Error file

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