HDLmaker was written by Joshua Rosen and Polybus Systems Corp, as an aid for the development of complex FPGA designs. It is offered free of charge, without warranty either expressed or implied. All comments, complaints or suggestions should be sent to bjrosen@polybus.com.

HDLmaker is an open source program. HDLmaker source code is included in the release. You are free to modify it and use it for your own purposes, however you may not include any HDLmaker source code in any commercial product without receiving written consent from Polybus Systems Corp. If you are interested licensing HDLmaker in whole or in part please contact us at bjrosen@polybus.com.

Polybus offers extensive hardware and software development services. For more information please contact bjrosen@polybus.com, or call (978)692-4828.

HDLmaker is copyright ©1994,1995,1996,1997,1998,1999,2000, and 2001 Polybus Systems Corp, Westford, MA.


  1. Overview
  2. Features
  3. Services
  4. Get the Software
  5. Installation
  6. Examples
  7. Getting Started
  8. Search Paths
  9. Using HDLmaker
  10. Running HDLmaker
  11. Top File Format
  12. Pin File Format
  13. HDLMaker Result Files
  14. Environment Variables
  15. Recompiling the Sources
  16. Resume for Joshua Rosen
  17. Other Links


HDLmaker is a tool for generating VHDL and Verilog FPGA designs. HDLmaker simplifies the development of complex FPGA designs as well as PC Boards by performing the following tasks:


Output can be targeted to either VHDL or Verilog.
Xilinx Virtex,VirtexE,4000E,4000EX,4000XL,5200,9500
Lucent ORCA 2C
Synopsys FPGA Compiler
Supports several simulators
Fintronics Finsim
Cadence Leapfrog
Cadence Verilog XL
Model Technologies (VHDL and Verilog)
HDLmaker generates an HTML version of the design with hyperlinks from all source files to generated files and from all component instances to the component's module.
HDLmaker based designs can be easily retargeted to different FPGA families, tools and languages, usually with a simple command line switch or with a single line in a source file.

Any supported synthesizer or simulator can be used without any additional work on the part of the user. HDLmaker generates all required Makefiles and Scripts automatically.

Translates PADS PCB files into VHDL.
Translates Scald Netlists into Verilog or VHDL

Services (Not free)

Polybus designs complex FPGAs in either VHDL or Verilog (your choice)
Polybus will customize HDLmaker to your environment:
Add conversions between any netlist format and either VHDL or Verilog including any custom attributes that are specific to your company.

Add support for other simulators and synthesis tools

Provide glue between different CAE tools.

contact: bjrosen@polybus.com
Resume: Joshua Rosen

Download Software (Includes all libraries, Linux Versions)

HDLmaker Version 5.6.0 (01/11/2001)


Installing Software

Untar it, then run the install script which will compile hdlmaker for your architecture.

tar -xvf hdlmaker_install.tar
cd hdlmaker_install



Getting Started

setenv HDLMAKER_LIB {/home/polybus/hdlmaker_lib}

if ( ! $?FPGA_FAMILY ) then

setenv FPGA_FAMILY virtex


The supported FPGA_FAMILYs are

if ( ! $?FPGA_NOXBLOX ) then



source $HDLMAKER_LIB/csh/hdlmaker.cshrc

hdlmaker -help all
hdlmaker sample.top

Library Search Paths

HDLmaker uses an optional file to specify the file search order. The file (called polybus.lib) must be placed in the local design directory.

Directories are searched in order starting with the local directory, followed by the directories in polybus.lib, and then the HDLmaker standard libraries.

The format of a polybus.lib entry is:

#design "library_name" "path"

Example polybus.lib

Using HDLmaker

HDLmaker has two major file types, these are:

Recompiling HDLmaker

Hdlmaker is supported on Linux, Solaris, and HP. To recompile it for any of these platforms, do the following:

cd $HDLMAKER_LIB/sources/hdlmaker_sources

make install
Other Links

Xilinx on Linux HOWTO


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